By the numbers: 20nm (and 40nm, 32nm, 28nm, and 14nm) design to be discussed in technical detail at next week’s CDNLive! conference in Silicon Valley

There’s still time to register for CDNLive!, which is being held on March 13 and 14 at the Doubletree Hotel in San Jose, California so let me give you a few numbers to whet your appetite: 40nm, 32nm, 28nm, 20nm, 14nm. Presentations at CDNLive! will provide successful strategies for working at each of these process nodes.

  • Samsung will be discussing In-Design DFM for 32/28nm
  • GLOBALFOUNDRIES will be discussing a 28nm design flow for analog and mixed-signal designs
  • ARM will be discussing a 22nm SOI test chip done in collaboration with IBM
  • IBM will be discussing the impact of double patterning at 20nm and 14nm
  • GLOBALFOUNDRIES will discuss parasitic extraction at 20nm
  • TI will discuss 28nm timing signoff
  • CSR will discuss variability due to layout-dependent effects at 40nm and 28nm
  • Cadence will also be discussing double patterning at 20nm

There’s still time to register! Click here.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in 14nm, 20nm, 28nm, 32nm, 40nm, CDNLive!, EDA360, Silicon Realization, SoC, SoC Realization, System Realization and tagged , , , , , , , , , , . Bookmark the permalink.

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