Richard Goering has written up last week’s EDA CEO panel, sponsored by EDAC (the EDA Consortium). The panel took place at the Silicon Valley Bank’s headquarters in Santa Clara, California and featured CEOs from four EDA companies—Cadence (Lip-Bu Tan), Gradient (Ed Cheng), Mentor Graphics (Wally Rhines), and Synopsys (Aart de Geus). It also included Simon Segars, Executive VP and General Manager of ARM’s Physical IP Division. Ed Sperling, Chip Design Magazine’s Editor-in-Chief of the System-Level Design community, moderated the panel of expert execs. I was there, but shooting video so I’m glad Richard was there to take notes. Here are some of the highlights:
IP/SoC Integration: Sperling suggested that IP integration was supposed to be as easy as snapping Lego blocks together, but it wasn’t turning out that way. He asked the panel members to comment. He also asked if we’d see larger blocks in the future. Segars said that there are a million and one wrong ways to put an SoC design together and that the biggest challenge was to make sure it’s done correctly. Inevitably, he said, we will see larger blocks. (One of the main topics of the Semico IMPACT Conference on May 16.)
Lip-Bu Tan noted that SoC design complexity is decreasing and that the design complexity now extends past the hardware. It also includes the software stack, which amplifies the complexity. Tan then said that the holistic complexity of hardware/software codesign and co-verification was one of the reasons that drove Cadence to articulate the EDA360 vision—as a means of recognizing where the effort is now needed for successful design. Nobody can say they have all the solutions, said Tan—we have to collaborate with different parties.
De Geus noted the extension of complexity at both ends of the Realization spectrum. At the device end, we’re “touching a lot more physics.” At the other end, “here comes all this software.” Then de Geus noted a common problem to illustrate the escalating difficulty of creating high-quality designs. Consider a mobile phone handset, he said. If it checks its location using the on-board GPS 14 times per minute, the battery will be drained in 20 minutes. The hardware design is good. The software works. But the overall system design is imperfect. It’s not hard to test for such a design defect, but first you need to realize what needs to be tested.
That comment led to a discussion of power consumption:
Power: It almost doesn’t need to be said that power is the number one issue with today’s advanced designs. I’ve written repeatedly about that issue in the EDA360 Insider. Lip-Bu Tan noted that power is a big concern within data centers because the electricity needed to power and cool these data centers is a significant portion of the ongoing operating cost for these data centers and data center architects are looking for a 5x or 10x reduction in power consumption for the servers, networking, and storage equipment in these centers. (For more elaboration on this point, see “Jan Rabaey’s remarkable short course in Low-Power Design Essentials, Part 1”)
Then Rhines jumped from the macro to the micro level. At small dimensions, he said, leakage has become significant and SoC designers looked to the EDA industry to solve this problem. The first step was to tweak the layout, said Rhines, then the RTL and now we’re tweaking the design at the system level by changing the architectures. Not said, but equally true, is that the operating software will also play a large role in reducing power consumption, per de Geus’ reference to the mobile phone and its battery-draining GPS discussed in his earlier remarks.
There was also some discussion about 3D IC assembly but I’ll wait for 3D Thursday to discuss those.
To read Richard’s complete blog on this panel discussion, click here.