EDPS (April 5-6) in Monterey tackles “Top EDA Problems” with speakers from Broadcom, Cadence, AMD, and Synopsys

Early next month in Monterey, California, the Electronic Design Processes Symposium will take on the “Top Five EDA Problems.” For the purpose of this event, these problems would appear to be DFT (design for testability), System-Level EDA, Parallel EDA, and runtime variance (Hmm, that seems to be four). Perhaps the audience will supply the fifth. Meanwhile, here’s the list of speakers for this segment:

  • Sri Ganta, Broadcom, “DFT at RTL”
  • Frank Schirrmeister, Cadence, “System-level EDA 2015”
  • Tom Spyrou, AMD, “Parallel EDA”
  • Sangeeta Aggrwal, Synopsys, “Runtime variance with NUMA architecture”

More information is here.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Silicon Realization, SoC Realization, System Realization and tagged , , , , . Bookmark the permalink.

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