3D Thursday: TSMC talks more about Moore, More than Moore, and 3D ICs at CDNLive!

Rick Cassidy, president of TSMC North America, gave a keynote speech at CDNLive! Silicon Valley this week and discussed 3D IC assembly in the context of Moore’s Law. “I think we can actually beat Moore,” he said after discussing planar IC development work at 14nm and 10nm. “3D design allows us to outpace Moore’s Law,” said Cassidy. It perpetuates scaling through innovative design. TSMC worked with Cadence on TSMC’s first silicon interposer vehicle and on the 3D IC design solution in TSMC’s Reference Flow 12 (see “Cadence Collaborates with TSMC on New 28-nanometer Flows”).

I’ve written about TSMC’s 3D plans before (see “3D Thursday: TSMC’s 3D plans and the word on 3D from Xilinx, Nvidia, IMEC, and STATS ChipPAC”) and Cassidy took this opportunity at CDNLive! to elaborate further. He discussed both 3D IC design and assembly and the use of silicon interposers (2.5D design and assembly).

For more on Cassidy’s talk, see Richard Goering’s writeup “TSMC CDNLive! Keynote – “We Can Beat Moore’s Law”) in his Industry Insights blog.

For information on a complete day of 3D IC technical discussion, see “EDPS 3D Friday (April 6) expands with new speakers including 3D IC assembly and packaging advocate Phil Marcoux


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 10nm, 14nm, 2.5D, 3D, CDNLive!, EDA360, Packaging, Silicon Realization, SoC, SoC Realization and tagged , , , , . Bookmark the permalink.

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