Dr. Venu Menon, VP of Analog Technology Development at TI, gave a deeply informative lunchtime keynote speech at this week’s ISQED Symposium. Most of Menon’s presentation discussed analog process technology: what’s important to analog chip design and manufacturing, what’s changed over the years, what are the differences between analog and digital IC processes, etc. However, one slide in particular caught my eye as a perfect topic for this week’s 3D Thursday. Here’s the slide:
In this slide, you can see a number of reasons to use a variety of 3D packaging schemes for analog chips. In the upper left corner, you can see two analog chips actually embedded in a circuit board. At the top, center, you see an extremely thin analog chip package designed to attach to the underside of another device. In this example, just below the top-center image, there’s an under-slung dc/dc converter that’s powering the chip sitting above it. Below that example in the center you see a complex 3D package that allows the analog chip to be closely coupled to a relatively large inductor. The two bottom images on the left and right seem to be more of the same.
Because this slide clearly shows an intersection between 3D IC assembly and analog chip technology—something usually not overly discussed in 3D IC technology coverage—I took the opportunity to interview Dr. Menon about analog and 3D at ISQED.
Menon said that analog chips can incorporate 3D assembly technology in a variety of ways. TSVs (through-silicon vias) can certainly be used as can more mature flip-chip and wire-bond technologies. When it comes to analog, said Menon, the question is “Can I buy a power/performance advantage using 3D interconnect?” It’s not a scaling discussion in the way it is for 3D assembly of digital ICs because analog device geometries tend to trail digital process nodes by several years—a topic covered in Dr. Menon’s keynote. Improving power consumption, performance, or lowering inductance using 3D interconnect technology are more important than scaling for analog technology.
For example, said Menon, take a high-speed analog device. You might use 3D IC assembly techniques to reduce the inductance of the electrical connections to that device. We do that today by using copper or gold wire bonds [instead of aluminum] for power and ground connections. However, TSVs can reduce the bond length for critical nodes by reducing the length of the connection to the chip’s bond pad from millimeters to microns. So that will be the first use for TSVs in analog chips he said, in high-speed analog components. And that application is not far off, he added. However, analog chips will need only ten to fifty TSVs, not the hundreds or thousands of TSVs needed for digital chips.
“First and foremost for analog,” reiterated Menon, “TSVs are a performance enabler.”
They can also enable new applications, he then added. For example, in wafer-scale chip packaging TSVs can permit the assembly of bare die with passive components such as inductors. When I seemed puzzled, Menon explained that it’s hard to attach a passive device to an unpackaged silicon die without the use of TSVs to anchor the passive component to the back of a chip yet that is the way some customers wish to buy the product. The TSVs become a package-free attachment method he said.
Then Menon summed up the 3D situation for analog. The 3D manufacturing process still needs work, he said. TI has done an internal analysis and concluded that the 3D assembly is not yet sufficiently mature for analog. If there’s no performance difference between a conventionally packaged assembly and a 3D assembly, then you will pick the approach with the lower price and 3D assembly is still more expensive in these early days. 3D is still not price competitive. However the cost will come down, he predicted.
“Analog guys will trail unless there’s a performance benefit,” concluded Menon.