There are more than 79,997 ways for your low-power design to fail. Want to learn how to avoid a nasty surprise? For free?

There are a range of low-power design approaches for ASIC design including:

  • Clock Gating
  • Multi-Voltage
  • Power Shutoff
  • Dynamic Voltage
  • Body Bias
  • Adaptive Voltage
  • All of the above

Used in combination, there are more than 80,000 possible low-power modes that all need to work. Consequently, they all need to be verified before you commit to silicon. You can learn about these modes and how to make sure you avoid nasty surprises when using these modes during a free Webinar sponsored by Cadence. The Webinar has a simple, direct theme: How to Avoid Low-Power Failures. John Decker, a system architect specializing in low-power design is the speaker.

Decker will cover:

  • Taxonomy of low-power techniques
  • Understanding the need for accuracy and completeness
  • Meaningful metrics enabling low-power measurements
  • Field-proven methods for flow automation

And here are four things you can expect to take away from this free Webinar:

1. Which low-power techniques are available

2. Tips and tricks for creating low-power designs

3. Automating a low-power flow from verification to implementation

4. Collecting measurements and reporting progress during the verification stage

The event takes place at noon EDT on April 4. Sign up here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in EDA360, Low Power, Silicon Realization, SoC, SoC Realization and tagged , , . Bookmark the permalink.

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