You have six weeks to wait for the Semico IP Summit. What will you do until then?

Use of IP in the design of SoCs has long been a fact. The very name “SoC” says that you’re using microprocessor IP at the very least. With that comes memory IP, memory controller IP, interface IP, analog IP, etc. With a push to the 28nm and 20nm by SoC vendors at the leading edge of the semiconductor wave are finding that it costs 2x the money to go from one process node to the next, according to Semico Senior Market Analyst Rich Wawrzyniak. In addition, says Rich, we’re now starting to see subsystem or “platform” IP take root—although you really don’t need a semiconductor industry analyst to tell you that. Just read the news.

If you need to sort all of this out, then you need to attend the Semico IMPACT IP Conference, taking place at the Doubletree Hotel in San Jose, California on May 16. The even includes a panel on the IP ecosystem and another panel on IP subsystems. Keynote speakers include:

  • Warren East, CEO of ARM
  • Grant Pierce, CEO of Sonics
  • Vishal Kapoor, VP of Product Management at Cadence
  • John Koeter, VP of Marketing at Synopsys

According to Wawrzyniak, the gold-plated sponsor list for the event includes:

  • AMD
  • ARM
  • Atrenta
  • Analog Bits
  • Cadence
  • GLOBALFOUNDRIES
  • Marcy NanoCenter at SUNYIT
  • Memoir Systems
  • Mentor Graphics
  • OCP-IP
  • Sonics
  • Synopsys
  • Tabula
  • TSMC
  • and Chip Design Magazine

Pre-registration is only $75. It’s $150 at the door. To register, click here.

For more information about the event, click here.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, IP, SoC Realization and tagged , , , , , , . Bookmark the permalink.

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