Last week at Design West in San Jose, Freescale demonstrated the first silicon realization of the low-power ARM Cortex-M0+ 32-bit RISC processor core in an engineering sample of the company’s brand-new Kinetis L microcontroller. (See “Freescale demonstrates first-pass Kinetis L silicon at Design West”) This week comes news of a free Webinar covering the technical details of the new ARM Cortex-M0+ processor core, which will be of interest to both hardware ASIC designers considering the core as an IP block to be included in a new design and to software developers who want to know how compatible the Cortex-M0+ core is with previous ARM Cortex-M cores.
You don’t have much time to register. The Webinar is April 5. Get going. Register here.