I really wanted to attend a paper titled “Why doesn’t my board work?” presented by John Milks, president of Cadence partner Adiva at CDNLive! held recently in Silicon Valley. My EDA roots are in pcb design, going back to my engineering work at Cadnetix back in the early 1980s, so I’ve got a soft spot for pcb design. But I missed the presentation, so Richard Goering has provided the next best thing to being there with his new blog post about that paper. It provides a lot of detail that you don’t want to miss if you’re involved in pcb design.
For example, Richard’s list of nine pcb design error causes sounds very familiar to me:
- Poorly defined design rules
- Warnings are not seen, or are ignored
- Mismatched revisions
- Checking not available or turned off
- Hiccups in data generation
- Rule set conflicts between software packages
- Mistakes in interconnect design
- Insufficient designer training
- Mistakes in part generation
There are some great graphical illustrations of design errors in the post as well. Check out Richard’s blog post here.
EDA360 Insider 
PCB design errors are an element of a bigger topic – design correctness. Design correctness is a combination of the logical design ( is the schematic correct? ) and the physical design ( is the PCB layout correct? ). Two PCB designs built off a common schematic can have very different performance outcomes based on the PCB design ( placement, routing, power, etc ). In other words, a logically correct design can still fail functional testing at the prototype phase. The challenge is to find a design verification solution that can thoroughly test (memory in particular) a prototype at speed and at different operating points. My experience is that many PCB designs go to software development and ultimately production with less than adequate functional test coverage ( i.e. holes in the test coverage). The outcome is unreliable hardware leading to some finger pointing between the hardware and software teams. Check out. http://www.kozio.com