3D preview from EDPS: Qualcomm’s Director of Engineering Riko Radojcic talks 3D and 3D EDA

Last week’s Electronic Design Process Symposium (EDPS) opened a rich new vein of 3D IC material and you’ll see a lot nuggets from me on that topic in the next few days. Meanwhile, Richard Goering has already published a post on his Industry Insights blog with a great overview of Riko Radojcic’s 3D presentation. Radojcic is the Director of Engineering at Qualcomm and has more than a passing interest in 3D IC assembly. Here are some of the high points:

  • 3D ICs are almost mainstream already. Many types of 2.5D and 3D assemblies are already being designed and 3D memory stacks are already in production.
  • Qualcomm is investigating stacks of memory and logic die, driven by the increasing costs associated with riding a 2D-only version of Moore’s Law.
  • Wide I/O DRAM provides much better power efficiency, scalable to higher memory transfer rates and bandwidths, than does LPDDR3 DRAM.
  • Stacking a pair of semiconductor die gives you about the same performance improvement as jumping to the next process technology generation.

Then Radojcic went on to detail the types of EDA tools he wants to support 3D IC design.

You really need to read Richard’s blog post for the details.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization and tagged , , , . Bookmark the permalink.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s