“3D IC test wafers will run this year and high-volume 3D IC manufacturing will start in 2013,” concluded Riko Radojcic at the end of his EDPS keynote on 3D ICs held in Monterey, California last Friday. Radojcic is Qualcomm’s Director of Engineering, so he just might know something about the state of 3D IC assembly although he’s not necessarily referring to Qualcomm in the above statement. His concluding remarks came at the end of an hour’s worth of hard-earned 3D IC assembly and design insights that Radojcic has assembled at Qualcomm. I’ve started at the end of his talk, so let me present his roadmap:
This image portrays the ultimate goal for 3D IC design. It shows three separate 3D IC stack types: a memory stack on the left, an analog/RF stack on the right, and a logic stack in the center. A 2.5D interposer joins and connects the three 3D stacks to a package substrate that also contains embedded devices. This is a truly complicated 3D semiconductor device.
Summarizing the last half of Radojcic’s presentation, there are presently a few problems with this device as envisioned:
- We can’t design it because we don’t have all the EDA tools we need.
- We can’t build it because the supply chain for assembling such a device is not yet sufficiently mature.
- We can’t test it because the test methodologies we currently use for 2D chips aren’t sufficient.
- We can’t cool it because we don’t know how except with water cooling through microchannels, which Radojcic said is too complex and too expensive except for high-end servers.
So we need to develop ways to get from where we are today to where we are going. And just where are we? According to the following image from Radojcic’s presentation, we’re in the package-on-package domain. Good current examples of package-on-package use include the Broadcom processor and SDRAM stack in the $25 Raspberry Pi single-board computer (see “3D Thursday: Raspberry Pi Foundation’s $25 ARM board boots Linux using stacked DRAM”) and the A5 application processor/LPDDR2 SDRAM stack in the Applie iPhone 4S (see “Apple iPhone 4S: How about a peek under the hood?”).
The next step up the complexity ladder connects logic die with memory die either through 2.5D interposers or using 3D Wide I/O DRAM stacks attached directly to a logic die. As stated several times in this blog (and more to come), Wide I/O DRAM offers compelling price, performance, and power benefits to system designers. (For example, see “Samsung DRAM combines 3D TSVs and wide I/O to move 12.8 Gbytes/sec. Is this the 3D revolution?”.) These price, performance, and power benefits are sufficient to drive the use of 2.5D and 3D (side-by-side and vertical) assembly techniques in applications where those benefits are required. The design and manufacture of mobile phone handsets are clearly one such application—one that Qualcomm is intimately familiar with. (Note: “TSS” in the above graphic stands for “through-silicon stacking” and denotes the use of through-silicon vias (TSVs) for 3D IC stacking.)
Ultimately, everything gets stacked by the time you reach the end of the above timeline.
“Why 3D?” asked Radojcic at the beginning of his talk. “Because 2D is getting awfully complicated.” In addition, 3D IC assembly is a way to integrate all of the divergent IC process technologies (logic, memory, analog, and RF) because we finally realize that the specialized process technologies (speed-optimized logic processes, cost-optimized memory processes, and analog-optimized—er—analog processes) aren’t going to mix on one die due to seriously conflicting requirements. 3D assembly permits such a mixing using optimized silicon processes but we need to be able to design for 3D before we can use it.
To do that, we need design tools.
In his recent blog post reviewing Radojcic’s talk, Richard Goering did a good job of summarizing the tools that Radojcic feels he needs:
- Pathfinding tools to create a “quick and dirty trial design to see what things are going to look like” (electrical, thermal, and mechanical die properties) with respect to 3D stacking. Such tools would also predict the interactions among stacked die while providing early estimates of area, power, and cost.
- Tech Tuning tools to bring 3D electrical, thermal, and mechanical considerations and interactions into the 2D IC design flow. Because complexity will escalate very quickly here, the tools need to be able to abstract the complex physical properties into simpler design rules that keep 2D die designers in safe areas without sacrificing too much power, performance, or cost.
- Thermal tools, because heat dissipation is a fundamental 3D constraint just as it is now a fundamental 2D constraint. For 3D IC assemblies, thermal issues must be solved at a system level because heat cannot easily be removed from die in the middle of a 3D stack “after the fact.”
- 3D Standards to help bring die from different design teams and different vendors together into 3D stacks. Radojcic noted that the Silicon Integration Initiative (Si2) is working on 3D design format exchange standards, Sematech is working on the process side, and “we really need interaction from the EDA community.”
How real is all of this. Well, refer back to the first paragraph of this blog post. Radojcic says that 3D IC assemblies will be in production (by someone) next year. (Of course, if you include the newest, largest Xilinx FPGA, 3D assemblies were in production last year; see “Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells, consumes only 20W”.) If that’s not sufficient, Radojcic also said that even Gartner now shows TSVs on the “Slope of Enlightenment” on its corporate Hype Cycle curve, and TSVs are now approaching the Gartner Plateau of Productivity.
What more proof could you want?
EDA360 Insider 