Networks on Chip: Redux, Redux, Redux

There must be some way out of here
Said the joker to the thief
There’s too much confusion
I can’t get no relief
– “All Along the Watchtower,” Bob Dylan

During the late 1980s and early 1990s, we had around ten annual “Year of the LAN” declarations. When it finally happened, Ethernet took over from the Babel of wannabe networking standards and we’ve not looked back. History is now repeating itself in miniature with Networks on Chip (NoCs), which have been discussed since at least 2001. I’ve been writing about NoCs since 2005. (See “NOC, NOC, NOCing on heaven’s door: Beyond MPSOCs—A report from the seventh-annual International Symposium on System-on-Chip design.”) Despite a few designs that employ NoCs, we’ve still not reached the point when I think we can declare the “Year of the NoC.”

Perhaps this year? There’s a very interesting paper to be given at DAC in June titled “Approaching the Theoretical Limits of a Mesh NoC with a 16-Node Chip Prototype in 45nm SOI” that has a lot of solid information in it. Perhaps this paper will provide more analytical support for the development of practical NoCs. The paper will be presented by Li-Shiuan Peh, an associate professor of electrical engineering and computer science at MIT.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Silicon Realization, SoC, SoC Realization and tagged , , , , , , , . Bookmark the permalink.

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