TSMC’s Executive Vice President and Co-Chief Operating Officer Dr. Shang-yi Chiang said at yesterday’s TSMC Symposium that the company will offer one process at the 20nm node, as reported by Dylan McGrath of EETimes. This position differs from the two- and three-flavor IC processes developed for earlier lithographic nodes (low-power, high-performance, and general-purpose). The reason is simple: there’s not that much performance or power difference between a 20nm high-k, metal-gate process tweaked for speed or for power.
For more general background information on the imminent 20nm node, see:
- ISQED Keynote: 20nm From a Custom/Analog Perspective
- Scaling the 20nm peaks to look at the 14nm cliff, Part 1: Tom Beckley from Cadence maps the challenges of advanced node design at ISQED
- Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm
- Want to know what’s going to happen at 20nm, 14nm, and beyond? A few answers from Frank Leu of Cadence
And don’t forget to sign up for the three free Cadence 20nm Webinars in May:
EDA360 Insider 