TSMC simplifies life at 20nm, will offer a single 20nm process technology

TSMC’s Executive Vice President and Co-Chief Operating Officer Dr. Shang-yi Chiang said at yesterday’s TSMC Symposium that the company will offer one process at the 20nm node, as reported by Dylan McGrath of EETimes. This position differs from the two- and three-flavor IC processes developed for earlier lithographic nodes (low-power, high-performance, and general-purpose). The reason is simple: there’s not that much performance or power difference between a 20nm high-k, metal-gate process tweaked for speed or for power.

For more general background information on the imminent 20nm node, see:

And don’t forget to sign up for the three free Cadence 20nm Webinars in May:

Looking at 20nm design? Three free Webinars can help.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 20nm, EDA360, Silicon Realization and tagged , , . Bookmark the permalink.

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