In a complete overhaul of its FPGA design tools, Xilinx has just announced the Vivado Design Suite for its current-generation 7 Series FPGAs (including the Zynq-7000 Extensible Processing Platform) and future FPGA generations. With this design-tool release, Xilinx is acknowledging the evolution of the FPGA from a logic-centric device to an IP-centric device capable of implementing relatively complex systems, in much the same way that gate arrays gave way to ASICs, SoCs, and then multi-processor SoCs (MPSoCs). Advanced-node FPGA silicon has evolved so the design styles and tools must also evolve. Xilinx started developing the Vivado Design Suite early in 2008 and trialed it with more than 100 of its customers before this production release.
The Vivado Design Suite consists of 16 individual tools ranging from an IDE (Integrated Development Environment) to an IP library, packager, and integrator; a high-level synthesis tool that accepts C, C++, and SystemC algorithmic block descriptions and converts them to Verilog or VHDL descriptions; a mixed-language simulator with hardware co-simulation capabilities for gate-level simulation; and an improved place-and-route engine based on an analytical solver rather than simulated annealing.
To me, the central focus of the Vivado Design Suite is clearly its use of IP as the central system building block. Advancing process nodes have made individual FPGA logic cells fade from the picture in much the same way that individual transistors have nearly vanished from advanced-node digital SoC designs. In both cases, a focus on IP-based design raises the design abstraction level so that the complexity of advanced-node silicon becomes manageable.
This emphasis on IP includes a heavy emphasis on ease of reuse to maximize the return on design investment. To that end, the Xilinx Vivado Design Suite includes an IP repository based on the XML-based IP-XACT standard and an IP packager that assists design teams in converting IP designs into IP-XACT format. An IP Integrator then permits assembly of IP blocks into subsystems and systems using a hierarchical design style that’s supported up and down the tool chain. Designers can use a graphical design tool for IP integration or a scripted approach using the Vivado IDE’s Tcl command language.
The Vivado Design Suite also includes a high-level synthesis tool called Vivado HLS that creates IP blocks from C, C++, and SystemC descriptions. SoC development teams have long known that algorithm designers prefer to create their algorithms in an implementation-agnostic manner, meaning they tend use software programming languages rather than hardware description languages. Vivado HSL can takes these descriptions and synthesize them into Verilog or VHDL descriptions.
This capability permits early functional simulation of algorithms using high-level language simulation instead of RTL simulation, which can run ten times faster due to the higher abstraction level. Faster simulation time provides more time for microarchitectural simulation as shown in this Xilinx video:
Xilinx is offering the Vivado Design Suite in three editions: the WebPack Tool, the Design Edition, and the System Edition. The WebPack Tool is a free, device-limited version. The $2995 Design Edition includes all tools other than the HLS high-level synthesis tool and the System Generator for creating and modeling DSP IP blocks. The $4795 System Edition includes all of the tools in the suite. Here’ s a chart clarifying the components in the three editions:
Xilinx will be demonstrating the Vivado Design Suite at DAC in San Francisco.