Do you need to improve verification performance for advanced-node SoCs? Learn how on May 14 in Munich.

The state space of a chip grows exponentially every 24 months. That’s the verification corollary to Moore’s Law. Verification engineers tackle the problem with faster simulation but that’s no longer enough. The complete verification cycle includes compilation/elaboration; RTL/gate/SV/e/SystemC mixed-mode simulation; and debug, analysis, and modification. There are also new verification techniques being added to the mix including algorithmic tuning, regression simulation, mixed-language/mixed-abstraction simulation, multi-core simulation, and project-level test optimization. You need help to keep pace with these new verification technologies and methodologies.

Help is here. Techtorial 1 of the Silicon Realization and Functional Verification track at CDNLive! EMEA covers the important aspects of improving verification performance for advanced-node SoCs. The session takes place on Monday, May 14 in Munich.

Register here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Silicon Realization, SoC Realization, System Realization, Verification and tagged , , , . Bookmark the permalink.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s