Optimizing ARM-based advanced-node SoCs at 28nm and 20nm? Learn how to optimize for power, performance, and area on May 14 in Munich.

Posted on April 25, 2012 by

Physical-aware synthesis and clock-concurrent optimization are two new ways to optimize your ARM-based advanced-node or mixed-signal SoCs for power, performance, and area (PPA). CDNLive! EMEA includes a Techtorial focusing on several methods of PPA optimization for ARM-based advanced-node SoCs at 28nm and 20nm. The session takes place on Monday, May 14 in Munich.

Register here.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 20nm, 28nm, ARM, EDA360, Silicon Realization, SoC, SoC Realization and tagged , . Bookmark the permalink.

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