Three free Webinars answer your questions on 20nm SoC design. What questions do you have?

What can you reasonably expect to get from 20nm?

What does it take to implement an ARM Cortex-A15 processor in 20nm?

What might come between you and success at 20nm?

How can you be more productive when creating 20nm designs?

These are some of the questions that will be answered in the Free Cadence 20nm Webinar series with technical experts from TSMC, ARM, Samsung, and IBM. The three Webinars include:

  • What it takes to enable foundry-optimized, higher-performance, lower-power designs at 20nm. Register here.
  • Experiences, best practices, and recommendations for 20nm success. Register here.
  • Addressing the challenges of 20nm design with double-patterning-aware analog and custom blocks and IP. Register here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 20nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization and tagged , , , , . Bookmark the permalink.

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