FREE Webinar on analog verification. Wednesday, May 9 at 9:00 am PST

Analog blocks are usually verified at the block level many things still go wrong with connectivity and control of the analog circuit at the SoC level. It’s not enough to integrate these analog blocks into digital simulations; you need to apply advanced digital verification methodology in the analog domain at the SoC level to know discover what’s wrong with the analog models in the discrete digital domain and gain the required amount of insight into key verification signoff metrics.

A new, FREE webinar from Cadence will discuss the connection between these domains and how to achieve analog block integration at any abstraction level (SPICE, AMS models, real number models). The Webinar will also discuss how to improve your verification quality and productivity using a metric-driven approach.

More information here.

Register here: Webinar #120509—Connecting SystemVerilog Real Numbers and Verilog-AMS Nets


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in Analog, EDA360, Mixed Signal, Silicon Realization, Verification and tagged , , , , , . Bookmark the permalink.

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