At DAC, take the path to successful 20nm design. The same path leads to breakfast. Wednesday, June 6

If you’ve been following along—or even if you haven’t—Cadence held three 20nm Webinars last week. Perhaps you have to see it in person before you believe it. Fair enough. Here’s your chance to hear first-hand how you can develop high-yielding 20nm designs at next month’s DAC in San Francisco from three companies with real expertise in the subject: Cadence, IBM, and Samsung. The opportunity comes with breakfast.

  • Date: Wednesday, June 6
  • Time: 8-9 am (breakfast starts at 7:30am)
  • Place: Moscone Convention Center, San Francisco, Rooms 270-276

First come, first served.

More info here.

Register here.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in 20nm, EDA360, IBM, Samsung, Silicon Realization, SoC, SoC Realization and tagged , , , . Bookmark the permalink.

Leave a Reply

Fill in your details below or click an icon to log in: Logo

You are commenting using your account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s