If you feel the urge to strut your stuff in front of a roomful of party-hearty DAC attendees, you’ve come to the right place. Applications are now open for the “EDA’s Got Talent” competition taking place on the Ruby Skye main stage during the DAC Denali Party (sponsored by Cadence). The four top acts will compete Tuesday evening, June 5. All four will get the adulation of an audience that’s generally feeling no pain by the time the competition ends and the voting begins. The winner gets a trophy and the right to perform the opening act at the Denali Party by Cadence during the 2013 DAC in Austin, Texas.
Search EDA360 Insider
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud2.5D 3D 3D IC 20nm 28nm 32nm 40nm Agilent Altera AMD Analog Android Apple ARM ARM architecture ARM Cortex-A15 ASIC Broadcom Cadence Canon Cortex Cortex-A15 Cortex-M0 DAC Dave Jones DDR3 DDR4 Double Patterning EDA EDPS Field-programmable gate array FinFET Flash Flash memory FPGA Freescale Freescale Semiconductor GlobalFoundries Google IBM Intel IP iPad iPhone JEDEC Jim Hogan Kinect Linux Low Power Lytro microcontroller Micron Microsoft Mixed Signal Multi-core processor Nvidia OrCAD pcb Printed circuit board Qualcomm Robot Samsung SDRAM Snapdragon SoC STMicroelectronics SystemC Texas Instruments TI TSMC USB verification video Wide I/O Xilinx
- 3D Thursday (early): Steve’s Improbable History of 3D ICs? Six decades of 3D electronic packaging
- 3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet
- 3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D
- 3D Thursday: How about a closeup of the Avago MiniPOD optical interconnect on the Altera Optical FPGA?
- Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- Cadence announces synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP
- 3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)
- 3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?
Download the EDA360 Vision Paper here: