FREE Webinar on the Challenges of 20nm design. Second in a 3-part series from Cadence

The second of a series of three Cadence Webinars on 20nm design is now archived and available for viewing if you missed the live event. You can read about this Webinar in Richard Goering’s blog (“Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology”), which discusses the major challenges in 20nm design and manufacturing including:

  • Manufacturability. More than 400 new advanced layout rules plus double patterning.
  • Timing Variability. Thinner wires cause increased coupling and signal integrity issues.
  • Design Size and Complexity. With 2x the number of gates per square micron, 20nm designs are more complex.

The Webinar speakers—Wei Lii Tan, senior product manager at Cadence, and Dr. Kuang-Kuo Lin, director of foundry design enablement at Samsung—tackle these three main challenges during the Webinar.

If you’d like to see it, you can still sign up. It’s FREE. Click here.

If you’d like to see the first Webinar in the new Cadence 20nm series, click here.

 

 

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 20nm, EDA360, Silicon Realization, SoC, SoC Realization and tagged , , , , . Bookmark the permalink.

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