You can change transistor threshold voltages on advanced-node designs just by placing them too near something else. (Scholarly paper with detailed analysis here.) You can solve this problem with overdesign but there are better ways. Layout-dependent effects and smart ways to mitigate them are the topics of a lunch discussion at DAC, being sponsored by Cadence and STMicroelectronics. During this discussion, you’ll learn what works—in practice. And yes, lunch is included.
- Date: Monday, June 4
- Time: 12-1 pm (lunch starts at 11:30am)
- Place: Moscone Convention Center, San Francisco, Rooms 270-276
First come, first served.