Moore’s Law: Wanted, Dead or Alive

Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held on April 26 at the Computer History Museum in Mountain View, California. Iyer pointed out that process complexity has grown from node to node. Yes we already knew that—but in earlier node transitions the increased processing cost was offset by the doubled number of additional transistors per unit area you get for each jump. Iyer projected a graph showing that the reduced effective cost per transistor stops falling after the 32/28nm node. Here’s the graph:

As you can see, transistor cost dropped in a fairly linear fashion from the 90nm node to the 32/28nm node but the cost is not dropping at the 20nm node or beyond.

Now please don’t get confused. You still get twice as many transistors per unit area at the 20nm node compared to the 28nm node. It’s just that the per-transistor cost isn’t falling and that trend’s expected to persist into the future.

Why? Iyer said, “There’s a lack of a viable litho strategy going forward.” In other words, 193nm light’s just run it’s course and litho costs have now gotten quite formidable. Now this has certainly happened before. The 180nm node, which dropped below the 193nm of the illumination source, required the adoption of phase-shift masks and we needed immersion lithography to get past the 65nm node. Each of these developments caused an incremental bump in litho costs—but nothing like 20nm.

So Iyer asked rhetorically, “Is there a problem?”

“Perhaps,” he answered, “but we have been here before…”

In 1990, we hit the limits of bipolar technology due to power limitations. Before that we had the “era of plenty” said Iyer. We switched to CMOS, a dark-horse candidate previously known to be a low-power process, but one that was exceedingly slow. The bipolar-to-CMOS jump was a big deal for the industry.

In 2000, we hit the limit for gate oxides based on silicon. Before that, we had the “era of Dennard Scaling” said Iyer. We switched to high-K, metal-gate transistors and added strain engineering. These changes have also been a big deal for semiconductor makers.

What we need now to address the imminent litho problems, said Iyer, is a solution that’s “orthogonal to the scaling path.” Iyer offered a few possible solutions including addressing the memory problem and 3D scaling.

IBM is addressing the problem of on-chip memory using eDRAM (embedded DRAM), which Iyer called “the gift that keeps on giving.” IBM is currently using an SOI process to build isolated, deep-trench capacitors that form the heart of its eDRAM cells. IBM Is already using eDRAM to selectively replace on-chip SRAM.

The cost of an SOI wafer adds less than 10% to the overall process cost and Iyer explained that IBM can replace all of the SRAM on a chip with eDRAM at no incremental cost if the on-chip RAM consumes at least 10% of the chip thanks to the die-area savings of eDRAM. As a bonus, deep-trench capacitors can be also used for on-chip decoupling.

Iyer then discussed 3D IC assembly. It does not eliminate the need for 2D scaling, he said. It’s an orthogonal element that increases performance and yields several system-level benefits:

  • Modularity
  • Better time to market
  • Better volumetric density
  • Lower power consumption because interconnect loads are smaller
  • Better performance because Z-direction latencies are smaller than for planar interconnect
  • Less complexity and lower system-level cost
  • Permits the integration of heterogeneous ICs, each optimized for a specific function

So with all of those benefits, is IBM looking into 3D IC assembly? If you’ve been reading the EDA360 Insider blog, you know the answer’s “yes.” (See “3D Thursday: Can IBM and 3M really build a 3D, 100-chip stairway to heaven with glue?”) Iyer added confirmation in the form of a photo showing a 32nm IBM chip with a TSV (through silicon via) and the deep-trench capacitors for eDRAM. Here’s the photo:

What is IBM likely to do with 3D and eDRAM technology? Well, Iyer immediately followed his discussion of 3D IC assembly technology with a slide on the Hybrid Memory Cube. (See “3D Thursday: Hybrid Memory Cube—Does anyone know what’s happening with IBM and Micron?“) He also showed this fascinating photo of an IBM mechanical demonstration vehicle of a 3D IC assembly with two processor chips mounted atop a 5-die stack of DRAM:

Iyer then concluded his GSA Silicon Summit keynote with these three points:

  • Lack of an effective litho solution is slowing raw Moore’s Law 2D scaling
  • We can no longer think of Moore’s Law as being limited to 2D scaling
  • Orthogonal scaling techniques such as eDRAM and 3D IC assembly will sustain the expectations we have for Moore’s Law

In other words, Moore’s Law is not dead yet but it is changing…again.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 20nm, 28nm, 32nm, 40nm, 65nm, EDA360, IBM, Low Power, Memory, Multicore, Packaging, TSV and tagged , , , , , , , . Bookmark the permalink.

2 Responses to Moore’s Law: Wanted, Dead or Alive

  1. george storm says:

    My take:

    3D assembly is a continuation of a denser-packaging trend that has been progressing in parallel with Moore. As such it is orthogonal to Moore, and cannot justifiably be treated as an addendum.

    To my mind, socalled integrated 3D (multiple active layers on a single die) could be regarded as dubious unless except in so far as it results in shared masking processes. However, we have in some sense been here before, as the number of metal layers also has had to be increased to cope with the increased complexity inherent in exploiting Moore.

    We are simulatnaeously losing one of what used to be the implicit benefits of Moore: clock speeds no longer increase intrinsically with process scaling; as things stand (even after Cu+lowK), the only way to increase speeds (at fixed circuit complexity) is to increase the number of interconnect layers to reduce interconnect capacitance.

    The other thing that looks to have fallen by the wayside is improving device yield as the process shrinks. FD SOI will give a few generations yet as regards parametric variability; however, reducing catastrophic defects (both production and wear-related) continues to be challenging(!)

    Is Moore’s law dead already? In the literal sense (number of transistors per die) almost certainly not, as human determination (using integrated active multilayer, additional metal layers, and, eventually, new lithographies) will allow density to increase for a few generations yet.
    Is Moore cost+speed -impact dead yet: I’d say temporarily, but integrated active multilayer should provide a generation or two of relief from (presently cost-dominant?) burgeoning density of interconnect. New lithographies may yet further extend cost impact – but you’d have to be very brave to bet your shirt on this.

    Oh, and did I forget to mention thermal budgets…?

  2. sleibson2 says:

    Thanks for leaving your perspective, George.

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