Richard Goering just published a detailed blog post about the TSMC 2.5D/3D IC test vehicle, which TSMC is calling CoWoS (Chip on Wafer on Substrate) in his Industry Insights blog. This approach to 3D IC assembly bonds active silicon die to entire wafers patterned with silicon interposers. The twist in this approach is that the die bonding occurs before any interposer thinning occurs to avoid warping and to give added strength to the assembly during most of the manufacturing process. TSMC takes ownership of the entire CoWoS chip manufacturing and assembly process and I am told that the yields are already pretty impressive, although I am not allowed to give you the actual number. It is impressive, however.
If you were at DAC, visited the Cadence booth, and looked very carefully, you would have seen the display sample of the first TSMC test vehicle in a display case. Cadence supplied design tools and helped refine the methodology for the TSMC CoWoS project, which is why the sample was in the Cadence booth at DAC. (See “Cadence Collaborates on 3D-IC Design Infrastructure with TSMC”) However, if you weren’t at DAC this week or if you didn’t happen to look in the right place, then here’s a photo I shot of the CoWoS test vehicle through the display case:
To read Richard Goering’s full blog post, see “TSMC-Cadence Collaboration Helps Clarify 3D-IC Ecosystem”