3D Thursday: My breakfast with IBM’s Gary Patton leads to a discussion of 20nm and 14nm IC design

Yesterday I moderated a panel on 2(x)nm success at DAC and one of the panelists was Dr. Gary Patton, VP of IBM’s Semiconductor Research and Development Center in East Fishkill, NY. I’ve heard Dr. Patton speak before and he knows a ton about what’s happening at the forefront of IC design and manufacturing. We spoke during breakfast before the panel. Actually, he talked and I tried to say as little as possible so as to maximize his part of the conversation. What I learned is really worth sharing.

I started out by asking about 14nm manufacturing. At one point, the industry position seemed to be that EUV (extreme ultraviolet, aka soft X rays) was essential to crossing over from 20nm to 14nm manufacturing. Not so, said Dr. Patton. Current optical lithography can certainly pattern 14nm features, you will just need more double patterning and perhaps triple patterning. In fact, said Dr. Patton, our 14nm strategy should not consider EUV essential but should take a position that EUV will be folded into the litho mix when it becomes economically viable.

Then Dr. Patton talked more about double patterning and erased yet another of my misconceptions. I had thought that double patterning at 20nm just involved perhaps the bottom-most one or two metal layers on a chip. In IBM’s world, there can be as many as ten or eleven metal layers so more expensive double patterning steps would be relatively limited and should not really affect manufacturing costs that much. Not so, said Dr. Patton. If you look at many current chips at the leading edge of manufacturing, double patterning is being used for as many as the first six or eight metal layers with larger feature sizes used in only the topmost few metal layers. Consequently, double patterning may have far more economic impact on 20nm chips that I (or perhaps you) expect.

During his short presentation at the beginning of the panel, Dr. Patton used this slide to discuss major changes in IC manufacturing over the last few decades and into the future:

As you can easily see from this slide, there’s a major upheaval in IC manufacturing about every 10 years. During the 1980s, bipolar technology reigned as the fastest process technology available. Planar CMOS took over when bipolar ICs started to draw too much power. By then, the shrinking lithographies allowed us to make faster CMOS devices; The rise in IC performance continued. At the end of the 1990s, we hit the scaling limits of conventional planar CMOS gate oxides and had to introduce new materials to add strain. We also had to adopt high-K metal gates to raise gate oxide thicknesses back up to a few dozen atoms because silicon oxide gates had gotten as thin as a completely impractical three atoms.

Today we seem to be at the end of the road for planar CMOS devices and are looking to move up in the third dimension in two ways. The first way is the adoption of 3D transistors (FinFETs), which promise performance advantages over planar CMOS transistors. The second way is the adoption of 3D packaging. The EDA360 Insider has covered both of these 3D development s regularly.

From Dr. Patton’s slide, it appears that 3D manufacturing will carry the industry for perhaps another decade. What lies beyond? There are several promising technologies, which led Dr. Patton to give semiconductor advances at least another two decades to run.

I hope to bring you the video of this DAC panel soon. It’s worth watching.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 14nm, 20nm, 28nm, Double Patterning, EDA360, EUV, Silicon Realization, SoC, SoC Realization and tagged , , , , , , , . Bookmark the permalink.

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