Some chip-design reality from Mentor’s Wally Rhines at last week’s annual DAC ESL panel

Last week at DAC, Mentor’s Chairman and CEO Wally Rhines chaired a panel on ESL but in his introduction, Wally spoke more about chip-design costs and associated software development. “The rapidly escalating cost of chip design has more to do with the cost of software development,” he said. Hardware (chip) development costs are holding their own and are up only about 10%. We’ve long acknowledged that the software-development teams are growing much faster than hardware-development teams. That’s the word I’ve consistently gotten from design leads for years, but you’d probably like some more qualitative support of that statement. Conveniently, Rhines provided this from an IBS study of four 28nm design projects. Here are the numbers:

Just eyeballing the chart, you can see that the software team is bulking up relative to the hardware team, based on these IBS numbers, and that differential growth is showing up in the overall costs, as you can see from this graph that Wally projected.

The data in this graph comes from the ITRS 2010 Roadmap cost chart and the dark bars are hardware-development costs for an SoC. The much bigger blue bars are the software costs. Get the picture? See the pain?

This chart explains why virtual prototyping is taking off. It’s says so more simply and more eloquently than the previous anecdotal information I’ve used in prior blog posts. It also conveys the picture more accurately than the indirect logic thread I’ve used lately that refers to the rising number of processors on each SoC.

More processors = more software. Where does that software come from?

There’s finally a very clear reason why the electronics industry needs to apply more automation to the development of software and to do what it can to move software development ever earlier in the development cycle.

It’s not an easy task, said Rhines. “Software engineers don’t use the same programming languages and they don’t write programs the same way [that hardware engineers do]” Rhines added that software developers tolerate nothing slower than the silicon, which is something that will certainly challenge EDA vendors.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, ESL, SoC, SoC Realization, System Realization and tagged , , , . Bookmark the permalink.

One Response to Some chip-design reality from Mentor’s Wally Rhines at last week’s annual DAC ESL panel

  1. Larry DiFrancesco says:

    While Wally Rhine spoke of design costs no one has mentioned how the yield effects the cost.
    Die testing appears to be after thought.
    Larry DiFrancesco 719-495-3424 Colorado springs. Co usa

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