Meaty new book on Mixed-Signal SoC Design, Verification and Implementation Methodology is nearly ready

Is your current SoC project a mixed-signal design? If not, chances are good that the next one will be. That’s because there’s been an evolution in SoC design from pure digital to analog/mixed-signal (AMS) designs over the past several years as integration levels soared. The first chapter of the soon-to-be-introduced book, the “Mixed-signal Methodology Guide” says: “Most SoCs currently being developed contain mixed-signal blocks such as phased locked loops (PLL), analog-to-digital converters (ADC) and digital-to-analog converters (DAC), high-speed input/output (I/O) interfaces, RF transceivers, memory interfaces and others.” Further, “Mixed-signal content, in most of today’s ICs and SoCs, has significantly increased from 10 to 20% to 50% or more due to increased needs for mobility, higher performance and integration of interfaces.”

Why is this important?

The combination of AMS and digital circuitry on one die complicates many matters. Let’s start with chip planning. AMS blocks are more sensitive to noise than digital circuits—far more sensitive in some cases. Let’s face it, that’s one reason why design teams often turn to digital solutions in the first place. Some approaches to system design involve getting the input signal(s) into the A/D converter as fast as possible.

But all-digital solutions can’t solve every design problem. We still need analog. And placing analog circuitry on the same chip with digital elements creates challenges with routing, power, timing, noise, and packaging—and all of these challenges put pressure on the overall SoC die size (and therefore cost).

As the first chapter of the new book says:

“…in designs requiring special routing for sensitive signals at the top level (buses, high-speed digital, analog, RF), blocks must be placed optimally to enable sufficient routing resources, avoid routing congestion and signal-interference problems. Similarly, special care needs to be given to placement of sensitive analog blocks because noise from digital switching can propagate through the package or substrate and impact the performance of the blocks or cause their complete malfunction. The conservative approach to chip planning, by increasing spacing, leads to increased chip area and reduced yield and profits.”

Then there’s design verification. That’s more complicated too. Here’s what the book’s first chapter has to say about this:

“Verification of analog circuits has traditionally been performed using SPICE (Simulation Program with Integrated Circuit Emphasis) simulation, capable of iteratively solving a set of nonlinear equations… The behavior of digital circuits is described using Boolean relations. Digital simulators execute much faster [than analog simulators such as SPICE] because they operate at higher levels of abstraction. When operating in an event-driven mode, evaluation is only performed when logic states change and do not require an iterative nonlinear equation solver. Simulating the behavior of a mixed-signal design requires both analog and digital simulators to work in parallel…”

“To address this mixed-signal verification, engineers have a few choices:

  • Simulate the entire mixed-signal design using a SPICE-type simulator at the transistor level. As design size increases, this approach is inadequate because a single simulation run could take days even with the fastest available simulator.
  • Simplify and model the analog part as a logic gate and use a digital simulator. Although sufficient to verify connectivity of the mixed-signal design, this approach is inaccurate for verifying interaction among analog and digital components.
  • Use mixed-signal simulation with analog at the transistor level and digital at the gate level. This approach is much faster than SPICE, but the analog solver limits performance for large designs.
  • Model analog using a behavioral language and simulate together with digital at the register transfer level (RTL) or even higher levels of abstraction. This approach enables simulation of the entire design as a system and solves simulation-performance issues. The only drawback is the required investment in analog behavioral modeling.”

Next, there’s mixed-signal testing. The cost of testing now exceeds the cost of die manufacture for some really complex mixed-signal SoCs so the test plan and the overall approach to testing are pretty important. The first chapter of the new mixed-signal methodology book has something to say about this as well:

“A common requirement is that the chip be testable on a commercial tester, regardless of the I/O or internal speed and regardless of the functions and mixed-signal content. To ensure testability, the device must include built-in test circuits, often increasing chip size by 10%, and in many cases includes redundancy for self-repair.

To test analog and mixed-signal portions of the design, the chip must include signal generators and measuring circuits… Test cannot be an afterthought and planning for test from the very beginning of the design process must be part of the design methodology in general, particularly for mixed-signal.”

If you’re getting the impression that mixed-signal SoC design is complex and that you might like some expert advice, then this blog post’s job is half done. The other half of the job is to refer you to the Web page where you can learn more about this remarkable new book, where you can sign up for an alert when it becomes available, and where you can download and read the first chapter for free.

You’ll find that Web page here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in Mixed Signal, Silicon Realization, SoC, SoC Realization and tagged , , , , , , , . Bookmark the permalink.

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