The Freescale Kinetis L microcontrollers based on the ARM Cortex-M0+ processor core: But what do they do???

A couple of days ago, I wrote that Freescale had announced that it was shipping alpha samples of its new Kinetis L microcontroller, which is based on the 32-bit ARM Cortex-M0+ processor core. (See “Freescale starts sampling $0.49 Kinetis L microcontrollers based on ARM Cortex-M0+ processor core”) I didn’t elaborate the features or uses of the microcontroller family in that blog post because the news was about shipping silicon. Nevertheless, I got a comment back chiding me about writing an advertisement for Freescale and not sufficiently explaining what these microcontrollers do. This blog post seeks to remedy that omission.

The Freescale Kinetis L microcontrollers are low-end, 32-bit microcontrollers. With their slimmed-down processor cores and restricted memory budgets, the members of the Freescale Kinetis L series are not going to boot Linux or Android. They target the lower-level tasks previously assigned to 8- and 16-bit microcontrollers in application niches including small appliances, gaming accessories, portable medical systems, audio systems, smart meters, lighting, and power control.

There are three sub-family groups in the Freescale Kinetis L series: the KL0, KL1, and KL2 groups. Here’s a block diagram of the KL0 sub-family:

On the left side of this diagram you see the 48MHz ARM Cortex-M0+ processor core which includes an interrupt controller and a debug interface. The ARM Cortex-M0+ debug facility deserves its own blog post but briefly it uses shared on-chip RAM for a trace buffer. Thus when you’re not using the RAM for debug (most of the time), that memory is available to the system.

How much RAM is there? Well, a quick look in the memory box shows that the Freescale Kinetis KL0 family comes with one to 4Kbytes of SRAM along with eight to 32Kbytes of Flash memory. According to the Freescale press release, the smallest member of this family costs $0.49 in 10K quantities.

All members of the KL0 microcontroller sub-family also include a DMA controller, an internal watchdog timer and a low-leakage wake-up unit, a 12-bit DAC and a 12-bit A/D converter, an analog comparator, a touch-sensor interface port, and various serial and parallel I/O ports. As you can see this microcontroller, like all members of the Freescale Kinetis L family, is very much a mixed-signal design.

Now here’s a block diagram of the Freescale Kinetis KL1 microcontroller sub-family:

The processor core and the system periperhals (DMA, watchdog, low-leakage wake-up unit) are the same as for the Freescale Kinetis KL0 parts. The memories are larger: four to 32Kbytes of SRAM and 32 to 256Kbytes of Flash. The A/D converter now operates as either a 12- or 16-bit converter and the D/A converter is optional as is the touch-sensing interface port. The analog comparator is still standard. There are more timers and serial interface ports in the Freescale Kinetis KL1 microcontrollers.

Finally, here’s a block diagram of the Freescale Kinetis KL2 microcontroller sub-family:

The Freescale Kinetis KL2 microcontrollers include the abilities of the Kinetis KL1 microcontrollers but add USB OTG (On-the-Go) capabilities for applications that need that sort of I/O capability.

For even more information, see this Freescale press release.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in Cortex-M0, EDA360, Mixed Signal, SoC, SoC Realization and tagged , , , , , . Bookmark the permalink.

Leave a Reply

Fill in your details below or click an icon to log in: Logo

You are commenting using your account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s