What effect does the ARM Cortex-M0 core have on mixed-signal microcontroller design?

Earlier this month at DAC, ARM, NXP, and Cadence hosted a panel on mixed-signal design as it applies to microcontroller design. Richard Goering posted a great summary of the topics discussed at the panel, but I want to tease out a few really juicy items from that discussion and talk about them here.

The first point I want to make here is about 32-bit processors in microcontrollers. Now 8-bit processors have been king of the microcontroller hill since the earliest days when the Intel 8048 (the 8051’s daddy!) and the Motorola 6801 first appeared. That was back in the late 1970s and a lot of 8-bit microcontrollers still ship today. But it’s undeniable that 32-bit processors, largely from ARM, have started appearing in more and more microcontrollers. Last time I counted, 20 microcontroller manufacturers were offering ARM-based microcontrollers!

Why?

Here’s the explanation from panelist Dominic Pajak, embedded segment manager at ARM:

“Microcontrollers typically have applications where [they] wake up, take a sensor reading, and go back to sleep. Processors in the Cortex-M range are able to do this in fewer cycles and effectively reduce the amount of the active duty cycle for the device. A communications stack typically has 32-bit addresses. Moving this around with an 8-bit microcontroller, an 8051 for example, is going to take more cycles, so the entire device is powered up longer.”

In other words, 32-bit microcontrollers get complex tasks done more quickly than 8-bit processors because they move or process more data per instruction. It’s pretty simple, isn’t it?

Here’s some additional information from panelist Rob Cosaro, Senior Director for Architectures and Systems at NXP:

“We’ve done a lot of benchmarking on code size, and we’ll see maybe a 50% reduction in code size running the same algorithm in M0 class processors compared to an 8051.”

So not only do 32-bit processors perform these more complex tasks in fewer instructions—therefore fewer instruction cycles—but the result is smaller code size too. Now code size has been one of the two real bugaboos for 32-bit processor core use in microcontrollers because on-chip code storage (usually Flash-based storage) actually consumes a lot of the die area. If 32-bit processors had much larger code footprints than 8-bit processors, then microcontrollers based on 32-bit processors would forever be at a cost disadvantage. But if 32-bit processors offer a code-space advantage, then there’s yet another reason to pick 32 bits over 8.

The same advantage applies to power consumption, as it so happens. Here’s Pajak again:

“Flash power can dwarf the processor power, so reducing the amount of flash activity goes a long ways to reducing the device power. In the Cortex-M architecture, versus 8-bit architectures, we’ve seen code size cut in half, with fewer instruction fetches from the Flash.”

You can read Richard Goering’s account of this DAC panel here.

NXP now offers several microcontrollers based on the ARM Cortex-M0 processor core. Read about them here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in ARM, Cortex-M0, EDA360, Low Power, Mixed Signal, SoC, SoC Realization, System Realization and tagged , , , , , . Bookmark the permalink.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s