Want details on the TSMC 20nm process technology?

Daniel Nenni has just published a great, short overview of the specifications for the TSMC 20nm process technology on his SemiWiki site. Nenni’s report hits the important benefits of the advanced process technology right at the beginning:

  • 30% faster
  • 1.9x density increase
  • 25% less power consumption

Nenni found the TSMC description of its 20nm process here.

Early last month at DAC, Cadence announced that TSMC had granted Phase I certification for both the Cadence Encounter RTL-to-GDSII digital flow and the Cadence Virtuoso custom/analog design platform for the TSMC 20nm design rule manuals (DRMs) and SPICE models.

Nenni concludes his writeup with this:

“As work continues to reach final 20nm certification in 2012, TSMC is supporting both EDA vendors and IP suppliers with design enablement kits. These kits facilitate continuous improvement and interaction between designers, the foundry; and tool and IP suppliers to prepare the 20nm design ecosystem for production success.”


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 20nm, TSMC and tagged , , , , . Bookmark the permalink.

1 Response to Want details on the TSMC 20nm process technology?

  1. Testchip says:

    This spec can beat Intel hardly.. 🙂

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