20nm design: What have we learned so far?

Even if you are not currently considering 20nm design, you owe it to yourself to download and read a new 9-page White Paper titled “A Call to Action: How 20nm Will Change IC Design” to learn about some tectonic shifts in the ways these new chips are being designed and fabricated. Early indications point to a 30-50% performance gain, 30% dynamic power savings, and 50% area reduction for 20nm chips compared to 28nm. Chip complexity may range up to 8-12 billion transistors. Consequently, the 20nm node will be compelling for many applications that demand the pinnacle of IC density, power, and cost. This is especially true in the consumer space. With its power, performance and area (PPA) gains, 20nm will enable a new generation of smaller, faster, more differentiated products in markets such as mobile computing, smartphones, servers, entertainment, and wireless equipment. Because of these advantages, the adoption of 20nm process technology is inevitable because…

Those who move to 20nm early will have a competitive advantage.

However, the 20nm node also raises significant new challenges for semiconductor design and manufacturing. The challenges require changes ranging from custom/analog cell creation to digital SoC integration. Based on experience, we already know that these challenges are manageable if EDA vendors, foundries, and IP providers work together to build 20nm-aware tools and automated flows.

Perhaps the most discussed 20nm manufacturing challenge is the need for double patterning. The EDA360 Insider has discussed double patterning several times over the past few months because double patterning has such a pervasive impact on 20nm silicon. Every step in the 20nm design flow must anticipate and prevent double patterning problems. Otherwise, the design project risks catastrophic schedule slippage and failure.

Here is a graphic example of why you need double patterning for 20nm design:

On the left, you see two significant problems—shorts—caused by a metal pitch that’s too small to handle reliably at 20nm with a single mask. On the right, you see the effect of using two mask patterns: no shorts.

Two types of double patterning are currently in use. Litho etch litho etch (LELE) or “pitch split” is the simplest and most intuitive double-patterning technique. Half the patterns go on the first mask and half go on the second mask. A coloring algorithm decides where to put each trace. Self-aligned double patterning (SADP) employs a technique called “sidewall image transfer.” It’s a more complex manufacturing process involving sidewall spacers. The payoff for the extra complexity is that SADP produces slightly better resolution than LELE1. SADP and LELE employ different design rules. The 20nm design tools must therefore understand both approaches.

Double patterning impacts every part of the IC design phase: standard cell development, placement, routing, extraction, and physical verification. It requires a correct-by-construction methodology in which every tool is double-patterning aware.

More specifically, double patterning places these requirements on design tools:

  • Cell and library generation must ensure that cells and IP blocks comply with double patterning design rules.
  • Placement must avoid potential color conflicts and minimize the area impact of double pattering while meeting timing, power, and routability requirements.
  • Routing needs a correct-by-construction approach with built-in awareness of 20nm and double patterning design rules.
  • Parasitic extraction must account for the impact of overlay errors on parasitics.
  • Timing and power analysis must handle a significant increase in multi-mode/multi-corner scenarios.
  • Physical verification tools need to ensure that the final decomposition is accurate and complete before handing off to the foundry.

The most important point here is that double patterning is not a magic ingredient to be added at the very end. It must be built into a 20nm-aware design flow from the very beginning.

However, the challenges presented by the 20nm node go far beyond double patterning. For example, 20nm chips will typically be very complex—with more than 100M gates—presenting severe challenges to synthesis and verification tools. Layout-dependent effects (LDE) due to lithography and stress engineering create timing and power variability. These too cause implementation and verification challenges. Hundreds of new and complex 20nm layout and manufacturing rules pose an implementation and signoff challenge.

To put things in perspective, there are around 5,000 design rule checks at 20nm, of which only 30 to 40 are for double pattering. There are roughly 400 new, advanced layout rules for metal layers alone.

Variability is everywhere at 20nm. Smaller CMOS devices, for example, are subject to variations in channel length and channel doping. As you might guess, even small amounts of variation at these feature sizes cause significant parametric variation.

Metal pitch reductions cause increased coupling between wires which leads to more and more difficult signal-integrity problems. Increased interconnect length and the need for more vias in long interconnects increases wire and via resistance. Consequently, design tools need to understand variable wire sizing and tapering techniques.

For custom/analog design at 20nm, parasitics and mismatches are already emerging as a key challenge. One reason for these particular problems is that more and more “noisy” digital control circuitry must be placed near sensitive analog circuitry. That shouldn’t be surprising when there are billions of transistors on the chip. It’s the desirable part of the added density at 20nm. However, at 20nm, where a device is placed in a layout and what is near to it can change device behavior.

This phenomenon is called “layout-dependent effects” (LDE), which has a big impact on a chip’s performance and power. While LDE was an emerging problem at 28nm, it is significantly worse at 20nm. As much as 30% of device’s performance can be attributed to the layout “context” at 20nm. That is, the neighborhood in which a device is placed. Consequently, 20nm characterization, placement, routing and analysis tools must be LDE aware.

As LDE demonstrates so well, what is unique about the 20nm node is the deep and complex interdependency of manufacturing and variability in addition to increasing timing, power, and area design challenges. To get these complex 20nm chips out the door, on time and within budget, IC design flows must undergo some significant changes.

One required change is that a sequential point-tool approach simply will not work. An integrated, end-to-end flow is required whether the goal is to mitigate design risks or to accelerate 20nm designs. Double patterning, clocking, and LDE must all be considered up front in the design flow. They must all be well understood and dealt with by the design tools, from IP characterization to final signoff.

To repeat: everything about 20nm design is interrelated and inter-dependent in complex ways. That is why the sequential point-tool approach won’t work.

Another key to success is tool automation. While digital design is heavily automated today, custom/analog design is not. Without more tool automation, it may take three times the effort to create custom/analog IP at 20nm compared to previous process nodes.

All of this enhanced, automated design requires more modeling to deal with the increased interdependencies. In digital and SoC design, the modeling technology must support different abstraction levels to provide just the right amount of detail for each task while efficiently and effectively dealing with the design challenges at each level in the design. Here’s a simplified block diagram of such a modeling approach that handles all levels from design exploration and planning to ECOs:

Finally, a correct-by-design approach—one that employs in-design signoff throughout the design flow—is critical. This sort of approach employs “signoff quality” engines for placement, routing, design for manufacturability, timing analysis, and signal-integrity analysis. In this sort of flow, each engine checks the work that’s been done before moving on. The alternative, leaving everything to a final signoff verification run, allows error to compound upon error until the very end. At that point, the combined set of errors—a hairball of a problem—may very well result in a design that is likely to be unfixable. That’s the downside of having so many transistors to work with at 20nm.

And that is the key reason to migrate to 20nm: increased design size and complexity. But this complexity is also one of the key challenges: 20nm designs will allow billions of transistors and many will have over 100 million gates.

Many 20nm chips will also require GHz performance, complex clocking schemes, and multiple power domains. At 20nm, everything impacts everything else. Power, performance and area must be considered concurrently. Clocking provides one example of the need for concurrent optimization. The traditional approach to clock tree synthesis (CTS) simply focuses on minimizing clock skew. CTS is usually separated from physical optimization.

A newer approach called “clock concurrent optimization” merges CTS with physical optimization. Observed results for this new approach include clock tree power reductions of 30%, clock-tree area reductions of 30%, and chip performance improvements of 100MHz for a GHz design that included ARM processor cores. As you can see, clock concurrent optimization is a very good match for the needs of 20nm digital design.

Finally, SoC design teams will integrate and verify large amounts of pre-existing analog and digital IP blocks in their 20nm designs. However, even with 80% IP reuse, there will still be a lot of new circuitry to design and verify. Consequently, there will be no alternative to using new design flows and higher levels of abstraction for 20nm IC design and verification.

Note: This blog was adapted from the White Paper titled “A Call to Action: How 20nm Will Change IC Design.” See the White Paper for even more details about 20nm design and verification.

For another take on the 20nm White Paper, see Richard Goering’s Industry Insights blog post “Whitepaper: 20nm is More Than Just Double Patterning.”


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 20nm, 28nm, AMS, Analog, ARM, Design Abstraction, EDA360, Silicon Realization, Verification and tagged , , , , , , , . Bookmark the permalink.

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