3D Thursday: Want some real-world insight into 2.5D and 3D IC design and assembly? Read on to get the word from Tezzaron Semiconductor

Ann Steffora-Mutschler just published an interview with Robert Patti, chief technology officer at Tezzaron Semiconductor, that gives some terrific technical detail about 2.5D and 3D IC design and assembly. Patti provides some rare insight into today’s (as in right now) 2.5D/3D state of the art through some really interesting qualitative and quantitative statements and some hard-to-find-but compelling numbers in this interview including these compelling statements:

  • “Sometimes you need to step back and look at it with a clean sheet of paper. We did that with our DRAM, and we recognized that if we did the process separation we could gain a lot of speed in the device. The speed could be used to reduce the number of circuits that did some of the operations because we could run them faster. We also could run them at lower voltages, so we just got more power efficiency there. It also allowed us to reduce the array sizes in the memory. The array size reduction improves reparability, but it also improves power because the rows and columns are shorter. And it’s a very different design at the end of the day because we started with a fundamentally different architecture. A lot of the miraculous gain from 3D is going to be from architectural changes.”
  • 2.5D and 3D “are similar. Generally speaking, the big difference is between 2.5 and 3D is the amount of interconnect and the level of efficiency. To the first order, 3D improves your I/O power by a factor of about 1,000; 2.5D improves it probably by about a factor of 50 to 100. So 2.5D gives you quite a bit of improvement, but it is limited in how much you can break things apart and segregate the functions.”
  • “We have really been spoiled because [the industry has] been doing it kind of the same way for 30 years where we just do the shrinks, and we kind of know how to do it, we have back-of-the-envelope calculations, we know how that next generation is going to work for us, pretty close. 3D—because it gives us a whole bunch of new knobs to turn—unfortunately makes it a much more complicated picture and I think what scares a lot of companies is they quickly realize that this isn’t going to be a back-of-the-envelope calculation.”

I commend Steffora-Mutschler’s article in the Low-Power High-Performance Engineering Community to your attention.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization and tagged , , . Bookmark the permalink.

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