Yesterday, Micron announced volume production of a new memory device containing one 1Gbit PCM (phase-change memory) die and one 512Mbit LPDDR2 SDRAM die. The two die reside in the device package as stacked die, with wire-bonded interconnect. This is a common form of 3D IC assembly that’s long been in use for mobile phone handset components to reduce component footprint and therefore printed-circuit board area. In this case, the design also reduces end-product manufacturing cost because the application processor needs only one interface and one controller to communicate with the PCM device and the SDRAM. There are also fewer printed-circuit traces to deal with using this approach. That’s an aspect of 3D IC assembly that I do not think is often discussed.
The PCM die and the SDRAM die share an LPDDR2 interface. That means that the PCM die employs the LPDDR2-NVM interface protocol. The device’s LPDDR2-NVM interface employs 400MHz, double-data rate transfers so the supported memory bandwidth is fairly high. One important end-product characteristic aided by this high bandwidth is boot time. It simply takes less time to get the boot code out of the PCM compared to NOR Flash memory.
For more in-depth coverage of this announcement, see “Want more details about the new Micron 1Gbit Phase-Change Memory / 512Mbit SDRAM device? Here are several.”
EDA360 Insider 