3D Thursday: Some unexpected implications of IP subsystems coupled with 3D IC assembly

A new “Experts at the Table” conversation on the Semiconductor Manufacturing and Design Community (SMD) site about IP Subsystems among Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries; Steve Roddy, vice president of marketing at Tensilica; Mike Gianfagna, vice president of marketing at Atrenta; Adam Kablanian, CEO of Memoir Systems; and led by Ed Sperling produced a short discussion about 3D IC assembly that bears repeating:

SMD: One of the great advantages of stacking die is that you don’t necessarily need to worry about developing IP at the latest process node. What does that mean for subsystems?

Roddy: If it becomes widespread then the economics of the value chain will change. That’s a dramatically different business model because the IP provider essentially is a contractual silicon provider. They might sell you a 50-cent sliver of silicon that you’re integrating, which is dramatically different business structure. The analog IP provider works to validate with the global partner. You could be sitting back at quarter micron for your analog and your memory might be at 14nm.

Gianfagna: There is certainly more predictability.

Roddy: It adds much more opportunity for the analog part, which has less flexibility because they have so many process-specific attributes. If you get it right, then there will be an emphasis on keeping it in that process.

Gianfagna: If you get it right for subsystems, you can make the same argument.

Roddy: You can still validate a piece of silicon with the proper interface. That may be the next evolution.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
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