On June 25, Cadence and EETimes Education and Training are sponsoring a training Webinar covering verification flows for SoC designs with PCIe and/or NVMe interfaces. The Webinar will cover:
- Verification pitfalls of the PCIe and NVMe interface protocols
- Best practices for verifying layered protocols such as PCIe and NVMe
- Metric driven verification techniques that shorten verification times
- Performance issues during verification
- Maximizing reuse of verification components for new generations interface specs
The presenters are Guoqing Zhang, Fellow and Verification IP CTO at Cadence, and Moshik Rubin, Senior Product Line Manager for Verification IP, at Cadence.
For more info, click here.
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