Want proof that Clock Concurrent Optimization produces real results?

I wrote about Clock Concurrent Optimization (CCOpt) a year ago (see “Clock Concurrent Optimization: The Primer to the Primer—OR—Want to overcome some major functional hurdles to Silicon Realization and save a lot of power on your SoC at the same time?”) and now Renesas has announced that its microcontroller designers have used that technology as part of the overall Cadence Encounter RTL-to-GDSII flow to knock out 30% of the power consumption in the company’s newest generation of 32-bit microcontrollers for the automotive market. Because the clock network can represent nearly a third of all of a microcontroller’s power consumption, whittling away at the power consumption of the clock network can produce a significant reduction in the overall power consumption of the device. The Renesas engineers achieved this reduction while meeting timing-closure and clock-delay requirements.

For even more technical information on Clock Concurrent Optimization, you might want to take a look at Richard Goering’s blog post “Why Cadence Bought Azuro – A Closer Look.”

You might also want to take a look at these two press releases:

Cadence Encounter Digital Technology Provides Ambarella With Big Improvements in Power, Performance and Area

Netronome Reaps Significant Power, Performance and Area Benefits with Cadence Encounter Digital Technology

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
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