Need to make an ARM Cortex-A9 processor core all it can be?

A new blog published today on the ARM Web site titled “How do you take an ARM POP up one more notch?” describes a very recent collaboration between ARM and Cadence to enhance the ARM POP IP, which helps any SoC design team maximize PPA (power, performance, area) results. ARM has offered its POP IP for a couple of years but this is the first time that the company has modified its POP IP for a specific EDA design flow.

The ARM POP IP discussed is specifically for an ARM Cortex-A9 processor core implemented in a TSMC 40nm process technology.

Not your specific processor core?

Not your chosen process technology?

Wait just a bit.

Note: For more info, see Richard Goering’s Industry Insights blog “ARM and Cadence Improve Cortex-A Power and Performance with Optimized Flow” and this article in EETimes by Peter Clarke.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 40nm, ARM, Cortex-A9, Silicon Realization, SoC, SoC Realization, TSMC and tagged , , , , . Bookmark the permalink.

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