This past weekend, the Web was abuzz with last week’s unveiling of Samsung’s Exynos 5 Dual mobile processor. This SoC features two 1.7GHz ARM Cortex-A15 processors rather than the previous Exynos generation Dual mobile processor that incorporated two 1.4GHz ARM Cortex-A9 processor cores. Between the ARM Cortex-A15 processor’s additional clock rate and its improved instructions/clock figure of merit (1.5x better for integer processing and 2x better for floating-point processing), Samsung says that the Exynos 5 Dual mobile processor has twice the processing bandwidth of the previous generation.
However, these two leading-edge CPU cores are not the only significant feature of this new mobile processor chip. It also includes a controller for 2560×2048-pixel WQXGA displays (also known as the “Wide Quad Extended Graphics Array”). Worst case, a WQXDA display controller operating at 60 frames/sec and 24 bits/pixel requires 8 Gbytes/sec of memory bandwidth. However, that’s with the display controller getting the entire memory interface. As the Samsung Exynos 5 Dual White Paper points out, assuming the display controller “only” takes 80% of the memory bandwidth, the chip will need 10 Gbytes/sec of memory bandwidth and that’s giving the two ARM Cortex-A15 processors a mere 2 Gbytes/sec of memory bandwidth to share.
Here’s a graph of display resolution versus memory bandwidth from the Samsung Exynos 5 Dual White Paper.
Consequently, the designers of the Exynos 5 Dual mobile processor added two 800MHz LPDDR3 memory controllers to the design. Together, these SDRAM controllers can generate a peak bandwidth of 12.8 Gbytes/sec of memory traffic between the Exynos 5 Dual mobile processor and the attached LPDDR3 1600 SDRAMs.
Here’s a block diagram of the Exynos 5 Dual mobile processor:
For more in-depth information on the ARM Cortex-A15 processor core, see:
To get your own copy of the Samsung Exynos 5 technical White Paper, click here.
(Note: This blog post originally appeared yesterday in the DenaliMemoryReport.com blog.)