Category Archives: 2.5D

EDPS 3D Friday (April 6) expands with new speakers including 3D IC assembly and packaging advocate Phil Marcoux

I’ve written previously about the all-3D IC design, assembly, and packaging program that will take place during the second day of the EDPS (Electronic Design Process Symposium) workshop in Monterey. This blog post is to let you know that additional … Continue reading

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3D Thursday (late): Qualcomm’s Riko Radojcic to keynote 3D Friday at EDPS in Monterey, April 6

EDPS—the world’s “best” conference devoted to discussing the processes needed for advanced electronic design—is dedicating its entire second day (Friday, April 6) to 3D IC topics. The just-announced keynote speaker is Riko Radojcic, Director of Design for Silicon Initiatives at … Continue reading

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3D Thursday: 40G and 100G optical Ethernet—Killer 3D app? Perhaps. Compelling? Definitely.

I’ve written several times about Wide I/O DRAM and how its speed and power advantages make it a slam dunk and killer app for 3D IC assembly. I saw another such 3D IC killer app this week at the Ethernet … Continue reading

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3D Thursday: EDPS conference features 3D Friday

The Electronic Design Process Symposium soon to be held in Monterey, California, will devote all of Friday, April 6 to 3D IC issues. There will be three morning presentations and a 5-person panel in the afternoon. The EDPS Program Web … Continue reading

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3D Thursday: Mark LaPedus writes overview of the 3D IC landscape

Briefly noted: Over at the Semiconductor Manufacturing & Design Community, Senior Editor Mark LaPedus has just published an article that’s a good review of the various challenges to 3D IC adoption including: Known good die Testability Design for test Standards … Continue reading

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3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work

I recently covered the groundbreaking WIOMING 3D chip design done by CEA-Imec in conjunction with ST-Ericsson. (See “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. … Continue reading

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GSA Silicon Summit to highlight cutting-edge IC technologies: 3D IC assembly, FinFETs, and SOI. April 26, Silicon Valley

The Global Semiconductor Alliance (GSA) is sponsoring a half-day event that will drill down into three of the leading-edge IC manufacturing technologies of the coming decade: 3D (and 2.5D) IC assembly, FinFETs (or Tri-gate FETs), and silicon-on-insulator (SOI) substrates. The … Continue reading

Posted in 2.5D, 20nm, 28nm, 32nm, 3D, EDA360, FDSOI, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , | 1 Comment

3D Thursday: Boosting the bandwidth of Wide I/O SDRAM to 1 Tbit/sec through standards evolution

This week’s DesignCon included a panel on 3D standards. You can read a review of the panel here in EETimes. Many topics were discussed, but the nugget I want to focus on in this blog post is the issue of … Continue reading

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3D Thursday: CEA-Leti launches Open 3D IC assembly partnership program

ElectroIQ reports that CEA-Leti in Grenoble has just launched an Open 3D IC program to permit companies more open access to the 3D IC assembly technologies developed at the research center. Last December, CEA-Leti and ST-Ericsson made a joint presentation … Continue reading

Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , , , , , | Leave a comment

3D Thursday: SEMATECH wades in to develop assessment criteria for 3D manufacturing equipment and processes

Earlier this week, SEMATECH—the global semiconductor industry’s research consortium—announced that it plans to conduct “Equipment Maturity Assessments (EMAs) of several critical 3D tools during 2012 to establish functional equipment capabilities and address high-volume manufacturing maturity issues” through its wholly owned … Continue reading

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3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it?

For the last 3D Thursday blog post of 2011in the EDA360 Insider, I thought I’d take a flight of fancy and try to put as many of this year’s 3D IC concepts as possible together to see what we might … Continue reading

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3D Week: The State of 3D IC assembly—December 2011

The nascent 3D IC industry’s foremost scribe, Francoise von Trapp, has just published a wrap up of this weeks 3D IC assembly conference held by the Research Triangle Institute in Burlingame, California. She notes some of the real highlights, which … Continue reading

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3D Week: Driven by economics, it’s now one minute to 3D

At last week’s IEEE 3D Workshop held by the local CPMT (Components, Packaging, and Manufacturing Technology) chapter, Dr Philip Garrou gave a presentation where he talked about the favorable economics of 3D and how those economics are now driving 3D … Continue reading

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3D Week: The three interconnect crises of the electronics industry and the inevitability of 3D. Believable?

Many people in the electronics industry view 3D IC assembly as not being in the mainstream. That’s easy to understand. It’s not at the moment. Yet I do believe in the inevitability of 3D assembly. Here’s why. At last week’s … Continue reading

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3D Thursday (OK, Friday): Live from Newport Beach—The IEEE 3D IC Workshop

I’m attending the all-day workshop on 3D ICs being held by the local IEEE Chapter of the CPMT (Components, Packaging, and Manufacturing Technology) Society and it’s a huge success with 150 attendees. I’m busy listening to presentations, but here’s a … Continue reading

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3D Thursday: A busy week coming up for 3D ICs

This is a very busy week for 3D in the world of the EDA360 Insider. I am about to board a plane for John Wayne Airport to attend an IEEE workshop on 3D IC assembly. Next Monday, there’s a meeting on … Continue reading

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3D Thursday: Is 2.5D IC assembly “buzz-worthy”?

I’ve written several times about the Xilinx Virtex-7 2000T FPGA that uses 2.5D IC assembly techniques to form four FPGA die into one FPGA package with two million logic cells. (See “3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers … Continue reading

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3D Thursday: Can we achieve true 3D IC manufacturing?

Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: … Continue reading

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3D Thursday: Who is responsible for successful 2.5D and 3D assembly? eSilicon is perhaps saying “Us”

Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: … Continue reading

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3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology

Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: … Continue reading

Posted in 2.5D, 28nm, 3D, 65nm, Silicon Realization, SoC, SoC Realization, TSV | Tagged , , , , | 2 Comments