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Category Archives: 28nm
Innovate or die! A high-tech parable from this week’s Time Magazine
Today I was reading this week’s issue of Time Magazine while eating lunch in my secret fish-and-chips restaurant at an undisclosed location in Milpitas, California when I chanced upon a fascinating article about RIM, maker of the BlackBerry. The article’s … Continue reading
Posted in 2.5D, 20nm, 28nm, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged Android, BlackBerry, FPGA, iPhone, John Roberts, RIM
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20nm design: What have we learned so far?
Even if you are not currently considering 20nm design, you owe it to yourself to download and read a new 9-page White Paper titled “A Call to Action: How 20nm Will Change IC Design” to learn about some tectonic shifts … Continue reading
This just out from DAC 2012: video interview with EDA bloggers Goering and Leibson on IP subsystems, 20nm, and more
Want to know what’s going to happen at DAC 2012? Oh, wait, that was a couple of weeks ago. Which is how long it took to get post this video of EDA bloggers Richard Goering and Steve Leibson from a … Continue reading
Posted in 20nm, 28nm, DAC, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged DAC, Design Automation Conference, Richard Goering, Steve Leibson
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3D Thursday: My breakfast with IBM’s Gary Patton leads to a discussion of 20nm and 14nm IC design
Yesterday I moderated a panel on 2(x)nm success at DAC and one of the panelists was Dr. Gary Patton, VP of IBM’s Semiconductor Research and Development Center in East Fishkill, NY. I’ve heard Dr. Patton speak before and he knows … Continue reading
Posted in 14nm, 20nm, 28nm, Double Patterning, EDA360, EUV, Silicon Realization, SoC, SoC Realization
Tagged Bipolar, CMOS, Extreme ultraviolet, FinFET, Gary Patton, IBM, Multiple patterning, TriGate
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Friday Video + 3D Thursday: Xilinx Virtex-7 H580T uses 3D assembly to merge 28Gbps xceivers, FPGA fabric
The first 3D part in the Xilinx Virtex-7 FPGA family—the 2000T—permitted the construction of a huge FPGA while sidestepping the yield issues of large 28nm die. Now, Xilinx has used 3D IC assembly to meld two FPGA logic slices and … Continue reading
Posted in 2.5D, 28nm, 3D, EDA360, FPGA, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 2.5D, 28Gbps, 3D, H580T, Xilinx
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Moore’s Law: Wanted, Dead or Alive
Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held … Continue reading
3D Thursday: GLOBALFOUNDRIES adds TSV capability for 28nm and 20nm die to Fab 8 in Saratoga County, New York
Customers’ clamor for 3D IC assembly capability and die with TSVs (through-silicon vias) has apparently gotten loud enough to cause a change of game plan for GLOBALFOUNDRIES, which announced today that it is spending “tens of millions of dollars” to … Continue reading
Optimizing ARM-based advanced-node SoCs at 28nm and 20nm? Learn how to optimize for power, performance, and area on May 14 in Munich.
Physical-aware synthesis and clock-concurrent optimization are two new ways to optimize your ARM-based advanced-node or mixed-signal SoCs for power, performance, and area (PPA). CDNLive! EMEA includes a Techtorial focusing on several methods of PPA optimization for ARM-based advanced-node SoCs at … Continue reading
Posted in 20nm, 28nm, ARM, EDA360, Silicon Realization, SoC, SoC Realization
Tagged ARM architecture, Munich
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Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm
This week at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote covering the industry’s challenges and progress at 20nm and … Continue reading
Posted in 10nm, 14nm, 20nm, 28nm, Design Abstraction, Design Intent, DFM, Double Patterning, EDA360, IBM, Silicon Realization
Tagged 10nm, 14nm, 20nm, 28nm, extraction, FinFET, ISQED, layout, parasitic
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Want to know what’s going to happen at 20nm, 14nm, and beyond? A few answers from Frank Leu of Cadence
Last week at the Global Technology Forum held at the Santa Clara Convention Center in Silicon Valley, Cadence VP of R&D Frank Leu discussed the things we’ve learned about 20nm IC manufacturing, what we are learning about 14nm, and where … Continue reading
Posted in 14nm, 20nm, 28nm, EDA360, Globalfoundries, Samsung, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 14nm, 20nm, 28nm, Cadence, IBM, In-Design, Samsung
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By the numbers: 20nm (and 40nm, 32nm, 28nm, and 14nm) design to be discussed in technical detail at next week’s CDNLive! conference in Silicon Valley
There’s still time to register for CDNLive!, which is being held on March 13 and 14 at the Doubletree Hotel in San Jose, California so let me give you a few numbers to whet your appetite: 40nm, 32nm, 28nm, 20nm, … Continue reading
Posted in 14nm, 20nm, 28nm, 32nm, 40nm, CDNLive!, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 14nm, 20nm, 28nm, 32nm, 40nm, CDNLive!, Double Patterning, Doubletree, GlobalFoundries, IBM, Samsung
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Friday Video: Common Platform Technology Forum reveals program agenda, rolls into Silicon Valley on March 14
The Common Platform partners are IBM, Samsung, and GLOBALFOUNDRIES and their annual Technology Forum rolls into Silicon Valley on March 14, so you have a couple of weeks to sign up. This short video from ChipEstimate.com gives you a good … Continue reading
Posted in 14nm, 20nm, 28nm
Tagged 14nm, 20nm, 28nm, Common Platform, GlobalFoundries, IBM, Samsung
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GSA Silicon Summit to highlight cutting-edge IC technologies: 3D IC assembly, FinFETs, and SOI. April 26, Silicon Valley
The Global Semiconductor Alliance (GSA) is sponsoring a half-day event that will drill down into three of the leading-edge IC manufacturing technologies of the coming decade: 3D (and 2.5D) IC assembly, FinFETs (or Tri-gate FETs), and silicon-on-insulator (SOI) substrates. The … Continue reading
Posted in 2.5D, 20nm, 28nm, 32nm, 3D, EDA360, FDSOI, Silicon Realization, SoC, SoC Realization
Tagged Cisco, FinFET, IBM, Intel, Multigate device, STMicroelectronics, Tri-Gate
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CDN Live covers the gamut of IC design on March 13 and 14 in San Jose. Register Now.
Registration for CDN Live—the 2-day technical conference for Cadence users being held on March 13 and 14 in San Jose—has just gone <er> live. Before I give you the link, I wanted to let you know about some of the … Continue reading
Posted in 20nm, 28nm, 32nm, CDNLive!, EDA360, Silicon Realization, SoC Realization, System Realization
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3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology
Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: … Continue reading
Posted in 2.5D, 28nm, 3D, 65nm, Silicon Realization, SoC, SoC Realization, TSV
Tagged 2.5D, 2000T, FPGA, SerDes, Xilinx
2 Comments
3D Thursday (early): Steve’s Improbable History of 3D ICs? Six decades of 3D electronic packaging
Last week at the 9th International SoC Conference in Newport Beach, I moderated a 3D IC panel that did a great job of exploring today’s state of the art for 3D IC development. I will be blogging the presentations made … Continue reading
What will EDA and chip design look like in the year 2020? Prognostications from the ICCAD panel
Last night, half a dozen ICCAD panelists attacked the topic “2020 Vision: What the recent history of EDA will look like in nine years.” That’s such a convoluted and hard-to-parse title that the panelists chose to discuss the state of … Continue reading
Posted in 20nm, 28nm, 3D, DAC, Design Abstraction, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged TSMC, Xilinx Virtex-7 2000T FPGA
4 Comments
Who wants more technical detail on the Altera SoC FPGA? Altera says…you!
After the previous post on the announcement of the Altera SoC FPGA ran in EDA360 Insider—see “The other shoe drops: Altera introduces SoC FPGA, mates ARM Cortex-A9 dual-core processor complex with FPGA fabric”—I heard from people at Altera. They wanted … Continue reading
Posted in 28nm, ARM, Cortex-A9, EDA360, SoC Realization, System Realization
Tagged Altera, Altera SoC FPGA, FPGA, HPS, SoC FPGA
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3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)
Tuesday, Xilinx announced that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, … Continue reading
Posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 2.5D, 3D, Amkor, FPGA, TSMC, Virtex, Xilinx
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Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)
Xilinx announced today that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, … Continue reading
Posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, TSV
Tagged 2.5D, 3D, Amkor, FPGA, TSMC, Xilinx
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Late breaking news: Freescale licenses ARM Cortex-A7 MPCore for future i.MX application processors and as a companion to previously licensed ARM Cortex-A15 MPCore.
Freescale has lost no time in announcing that it has licensed the just-announced ARM Cortex-A7 MPCore processor for its i.MX series of application processors. According to the Freescale press release: “Freescale plans to incorporate ARM Cortex-A7 and Cortex-A15 processors in … Continue reading
Posted in 28nm, ARM, Cortex-A15, Cortex-A7, EDA360, Silicon Realization, SoC, SoC Realization
Tagged ARM Cortex-A7, Cortex-A15, Cortex-A7, Freescale
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ARM drops Cortex-A7 core on unsuspecting market, devastates low-power SoC and application-processor landscapes. What’s it all mean?
ARM has just announced the ARM Cortex-A7 processor core for SoC designers and the low-power landscape will never be the same again. Why? Because the Cortex-A7 core implemented in a 28nm process technology is reportedly one fifth the size of … Continue reading
Where’s the sweet spot for IC process technology right now? Semico has an answer
Semico just released its latest wafer demand report for 2011 and the top-line conclusion isn’t wonderful but it’s not horrible either. Unit sales and wafer demand in the electronics industry will be up for the year but falling ASPs mean … Continue reading
The other shoe drops: Altera introduces SoC FPGA, mates ARM Cortex-A9 dual-core processor complex with FPGA fabric
It’s been more than a year and a half since Xilinx first started to talk publicly about the fusion of processors and FPGAs—a product now known as Zynq. It seemed inevitable that Altera would eventually counter with a competing product … Continue reading
Posted in 28nm, ARM, EDA360, Silicon Realization, SoC, SoC Realization
Tagged Altera, Cortex-A9, FPGA, Xilinx, Zynq
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Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
As I reported by the EDA360 Insider more than two months ago—see “Qualcomm renames existing ARM-based Snapdragon mobile application processors and provides future roadmap”—Qualcomm has been discussing the 28nm version of its Snapdragon mobile SoC, called the Snapdragon 4. Now … Continue reading
Posted in 28nm, ARM, EDA360, Silicon Realization, SoC, SoC Realization
Tagged GPU, Graphics processing unit, Krait, Nvidia, Qualcomm, Snapdragon, Wi-Fi
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