Category Archives: 3D

3D Thursday: Practical Approaches to 3-D IC—TSV/Silicon Interposer and Wide IO Implementation From People Who Have Been There, Done That

If you’re like me, you’ve heard more than enough theory about 3D IC assembly and you’re ready to get on with the main event and design something. Want to hear about 3D IC technology that works? Now? Then you will … Continue reading

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3D Thursday: GLOBALFOUNDRIES adds TSV capability for 28nm and 20nm die to Fab 8 in Saratoga County, New York

Customers’ clamor for 3D IC assembly capability and die with TSVs (through-silicon vias) has apparently gotten loud enough to cause a change of game plan for GLOBALFOUNDRIES, which announced today that it is spending “tens of millions of dollars” to … Continue reading

Posted in 20nm, 28nm, 3D, EDA360, Globalfoundries, Silicon Realization, SoC, SoC Realization, TSV | Tagged , , , , , , | Leave a comment

3D Thursday: Qualcomm’s Nick Yu says “3D DRAM stacking has started—it’s shipping in products”

Today’s GSA Silicon Summit held at the Computer History Museum in Mountain View, California included a talk on 3D IC assembly by Nick Yu, VP of Engineering, VLSI Engineering, at Qualcomm. Yu is in charge of Qualcomm’s technology roadmaps including … Continue reading

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3D Thursday: The low down on low-power CPU-memory connections from EDPS

Earlier this month at EDPS, Marc Greenberg, Director of Product Marketing for the Cadence Design IP Group, said that Wide I/O SDRAM memory was going to drive the earliest adoption of 3D IC assembly techniques. Not simply because Wide I/O … Continue reading

Posted in 2.5D, 3D, EDA360, Memory, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , | Leave a comment

3D Thursday: A funny thing happened to me on the EDPS 3D-IC panel

Last Friday, I moderated an all-star, hand-picked 3D-IC panel at the Electronic Design Process Symposium (EDPS) in Monterey, California. The panel included: Phil Marcoux, Managing Director, PPM Associates, experienced packaging expert Herb Reiter, President of eda2asic, Chair of the Global … Continue reading

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Want a peek at a possible Qualcomm 3D IC roadmap?

“3D IC test wafers will run this year and high-volume 3D IC manufacturing will start in 2013,” concluded Riko Radojcic at the end of his EDPS keynote on 3D ICs held in Monterey, California last Friday. Radojcic is Qualcomm’s Director … Continue reading

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3D preview from EDPS: Qualcomm’s Director of Engineering Riko Radojcic talks 3D and 3D EDA

Last week’s Electronic Design Process Symposium (EDPS) opened a rich new vein of 3D IC material and you’ll see a lot nuggets from me on that topic in the next few days. Meanwhile, Richard Goering has already published a post … Continue reading

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3D Thursday: Micron to present Hybrid Memory Cube status at EDPS in Monterey, April 6—there’s a lot of news

I’ve already written many blog entries about the Micron Hybrid Memory Cube (HMC), a 3D stacked memory device that can deliver a theoretical DRAM bandwidth of 128Gbytes/sec to a host system using a 4-die stack of DRAM (NOT SDRAM) on … Continue reading

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3D Thursday: A quick look at glass interposers for 3D IC assembly

3D InCites just published a short piece on glass interposers for 3D ICs, as discussed at the 2012 IMAPS International Device Packaging conference, held March 5-8 in Scottsdale, AZ. If you’re interested in seeing a more technical presentation on the … Continue reading

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3D Thursday: 3D ICs and analog chips. Where’s the match? Is there a match?

Dr. Venu Menon, VP of Analog Technology Development at TI, gave a deeply informative lunchtime keynote speech at this week’s ISQED Symposium. Most of Menon’s presentation discussed analog process technology: what’s important to analog chip design and manufacturing, what’s changed … Continue reading

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3D Thursday: TSMC talks more about Moore, More than Moore, and 3D ICs at CDNLive!

Rick Cassidy, president of TSMC North America, gave a keynote speech at CDNLive! Silicon Valley this week and discussed 3D IC assembly in the context of Moore’s Law. “I think we can actually beat Moore,” he said after discussing planar … Continue reading

Posted in 10nm, 14nm, 2.5D, 3D, CDNLive!, EDA360, Packaging, Silicon Realization, SoC, SoC Realization | Tagged , , , , | Leave a comment

EDPS 3D Friday (April 6) expands with new speakers including 3D IC assembly and packaging advocate Phil Marcoux

I’ve written previously about the all-3D IC design, assembly, and packaging program that will take place during the second day of the EDPS (Electronic Design Process Symposium) workshop in Monterey. This blog post is to let you know that additional … Continue reading

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3D Thursday: How about a closeup of the Avago MiniPOD optical interconnect on the Altera Optical FPGA?

I just posted a blog entry about the Altera Optical FPGA that pumped 100Gigabit/sec Ethernet (GbE) traffic through a 3D-package-on-package-mounted, 12-channel optical interconnect device from Avago. (See “3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle … Continue reading

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3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet

This week at the Optical Fibre Communication Conference and Exposition (OFC) in Los Angeles, Altera demonstrated a specially modified Stratix IV FPGA that handled bidirectional 100Gbps Ethernet (100GbE) traffic over a pair of IC-package-mounted Avago MicroPOD multi-lane optical transceivers. The … Continue reading

Posted in 3D, EDA360, Packaging, Silicon Realization, SoC, SoC Realization | Tagged , , , , , | 2 Comments

Tales from the EDA CEOs: The EDAC panel talks about IP and SoC integration, power, and other topics

Richard Goering has written up last week’s EDA CEO panel, sponsored by EDAC (the EDA Consortium). The panel took place at the Silicon Valley Bank’s headquarters in Santa Clara, California and featured CEOs from four EDA companies—Cadence (Lip-Bu Tan), Gradient … Continue reading

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Less than two weeks left for early-bird EDPS registration. Don’t miss 3D Friday, the other EDA speakers, or your chance to network for that matter

EDPS (The Electronic Design Process Symposium) provides a dynamic venue for the exchange of ideas among the top thinkers, movers, and shakers in EDA, who focus on how chips and systems are designed in the electronics industry. Attendees of this … Continue reading

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3D Thursday: Three on 3D—papers from ISSCC

San Francisco Tech writer Rik Myslewski just published a long article on the UK’s “The Register” Web site covering three 3D papers given at last week’s ISSCC. The papers were presented by IBM (“3D system prototype of an eDRAM cache … Continue reading

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3D Thursday (Leap Year edition): Raspberry Pi now on sale, Feb 29

The Raspberry Pi foundation has announced that you can now order the Raspberry Pi Model B—a $35 single-board computer—from its distributors: Premier Farnell (Element14 in the US) and RS Components. If you’re not familiar with the RaspBerry Pi board, it’s a … Continue reading

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3D Thursday (late): Qualcomm’s Riko Radojcic to keynote 3D Friday at EDPS in Monterey, April 6

EDPS—the world’s “best” conference devoted to discussing the processes needed for advanced electronic design—is dedicating its entire second day (Friday, April 6) to 3D IC topics. The just-announced keynote speaker is Riko Radojcic, Director of Design for Silicon Initiatives at … Continue reading

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3D Thursday: 40G and 100G optical Ethernet—Killer 3D app? Perhaps. Compelling? Definitely.

I’ve written several times about Wide I/O DRAM and how its speed and power advantages make it a slam dunk and killer app for 3D IC assembly. I saw another such 3D IC killer app this week at the Ethernet … Continue reading

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3D Thursday: EDPS conference features 3D Friday

The Electronic Design Process Symposium soon to be held in Monterey, California, will devote all of Friday, April 6 to 3D IC issues. There will be three morning presentations and a 5-person panel in the afternoon. The EDPS Program Web … Continue reading

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3D Thursday: Is Wide I/O SDRAM free for the end user???

A recent email from Marc Greenberg, Director of Product Marketing for the Cadence Design IP Group, suggested that Wide I/O used in a 3D stack is free for the end user. In other words, there’s no incremental cost in the … Continue reading

Posted in 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , , , | Leave a comment

3D Thursday: Mark LaPedus writes overview of the 3D IC landscape

Briefly noted: Over at the Semiconductor Manufacturing & Design Community, Senior Editor Mark LaPedus has just published an article that’s a good review of the various challenges to 3D IC adoption including: Known good die Testability Design for test Standards … Continue reading

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3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work

I recently covered the groundbreaking WIOMING 3D chip design done by CEA-Imec in conjunction with ST-Ericsson. (See “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. … Continue reading

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GSA Silicon Summit to highlight cutting-edge IC technologies: 3D IC assembly, FinFETs, and SOI. April 26, Silicon Valley

The Global Semiconductor Alliance (GSA) is sponsoring a half-day event that will drill down into three of the leading-edge IC manufacturing technologies of the coming decade: 3D (and 2.5D) IC assembly, FinFETs (or Tri-gate FETs), and silicon-on-insulator (SOI) substrates. The … Continue reading

Posted in 2.5D, 20nm, 28nm, 32nm, 3D, EDA360, FDSOI, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , | 1 Comment