Category Archives: 65nm

Moore’s Law: Wanted, Dead or Alive

Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held … Continue reading

Posted in 20nm, 28nm, 32nm, 40nm, 65nm, EDA360, IBM, Low Power, Memory, Multicore, Packaging, TSV | Tagged , , , , , , , | 2 Comments

Freescale demonstrates first-pass Kinetis L silicon at Design West (The conference formerly known as the Embedded Systems Conference)

Two weeks ago, ARM introduced its new low-end Cortex-M0+ 32-bit processor core. At the same time, Freescale announced that it was planning on introducing a new line of Kinetis “L” low-power microcontrollers based on the ARM Cortex-M0+ processor. (See “How … Continue reading

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Posted in 65nm, AMS, ARM, Cortex-M0, EDA360, Firmware, Silicon Realization, SoC, SoC Realization | Tagged , , | Leave a comment

3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology

Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: … Continue reading

Posted in 2.5D, 28nm, 3D, 65nm, Silicon Realization, SoC, SoC Realization, TSV | Tagged , , , , | 2 Comments

ExtremeTech.com provides some lessons to be learned from the Google Nexus One smartphone’s system-level design and Android 4.0—Ice Cream Sandwich

Ryan Whitwam at ExtremeTech.com has written another insightful article on System Realization as it relates to the Google Nexus One smartphone’s supposed inability to run Ice Cream Sandwich (ICS), the latest and soon-to-be-introduced version of the Google Android OS. As … Continue reading

Posted in 65nm, Android, ARM, EDA360, Ice Cream Sandwich, SoC Realization, System Realization | Tagged , , , , , | Leave a comment

3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)

Tuesday, Xilinx announced that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, … Continue reading

Posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , | Leave a comment

Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)

Xilinx announced today that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, … Continue reading

Posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, TSV | Tagged , , , , , | Leave a comment

Where’s the sweet spot for IC process technology right now? Semico has an answer

Semico just released its latest wafer demand report for 2011 and the top-line conclusion isn’t wonderful but it’s not horrible either. Unit sales and wafer demand in the electronics industry will be up for the year but falling ASPs mean … Continue reading

Posted in 20nm, 28nm, 65nm, EDA360, Silicon Realization | Tagged | Leave a comment

Experimental , ultra-low-power 1.2V, 65nm SoC from ST and MIT operates at 82.5MHz (!) maximum, 540KHz at 0.54V

Last week, ST Microelectronics and MIT’s Microsystems Technology Laboratory announced the development of a low-power 65nm SoC that operates an on-chip microprocessor core at supply voltages as low as 0.54V and the on-chip SRAM with supply voltages as low as … Continue reading

Posted in 65nm, EDA360, Low Power, Silicon Realization, SoC, SoC Realization | Tagged , | Leave a comment