Category Archives: DAC

3D Thursday: Wide I/O and TSVs have a ripple effect on the DRAM controller. Who knew?

Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments … Continue reading

Posted in 2.5D, 3D, DAC, EDA360, IP, Silicon Realization, SoC, SoC Realization, System Realization, TSV, Wide I/O | Tagged , , , , , | Leave a comment

Friday Video: EDA360 Insider talks HW/SW Codesign and Xilinx Zynq Dev Board with ChipEstimate.TV at DAC

I spent a few minutes with Sean O’Kane of ChipEstimate.TV at DAC earlier this month talking about system design, HW/SW codesign, and the new Avnet Dev Board for the Xilinx Zynq-7000 EPP. Here’s the video:

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This just out from DAC 2012: video interview with EDA bloggers Goering and Leibson on IP subsystems, 20nm, and more

Want to know what’s going to happen at DAC 2012? Oh, wait, that was a couple of weeks ago. Which is how long it took to get post this video of EDA bloggers Richard Goering and Steve Leibson from a … Continue reading

Posted in 20nm, 28nm, DAC, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , | Leave a comment

3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—“Learn to work together”

Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about … Continue reading

Posted in 2.5D, 3D, DAC, EDA360, Low Power, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , , , , , , | 5 Comments

Tuesday DAC Photos: Cool Shoes and the transit of Venus across the Sun

Here are two photos from today’s DAC in San Francisco. The first photo is a pair of shoes worn by Susan Peterson of Cadence. We were told to wear black shoes for our show “outfit.” Too bad no one said … Continue reading

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Gary Smith proposes a 3-layer taxonomy for platform-based SoC design—Live from DAC 2012

EDA’s chief analyst Gary Smith is high on IP subsystems—big ones. Only Gary calls them platforms. Why is Smith so enthusiastic? Because, as he says, he was wrong last year in his estimates of how much it costs to develop … Continue reading

Posted in DAC, IP, SoC, SoC Realization, System Realization, Texas instruments | Tagged , , , , , , , , | Leave a comment

DAC 2012: Get answers to all of your EDA questions at 78 Cadence demo suite slots

Next week (Monday, Tuesday, and Wednesday) you can get all of your EDA questions answered at the Cadence DAC demo suites. There are 78 demos over the three days covering the following EDA topics: Mixed-signal and low-power design RTL-to-GDSII design … Continue reading

Posted in DAC, EDA360, Low Power, Mixed Signal, pcb, Silicon Realization, SoC, SoC Realization, System Realization, TLM, Verification, VIP, Virtual Prototyping | Tagged , , , , , | Leave a comment

Beyond breakfast: An ethical bribe for attending “The Path to Yielding at 2(x)nm and Beyond” at DAC

Yesterday, I wrote about a terrific discussion panel about the challenges of 20nm design at DAC. I am moderating the panel and there will be speakers from the Common Platform partners including IBM, Samsung, GLOBALFOUNDRIES (just confirmed!), and Cadence. (See … Continue reading

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At DAC: The path to 20nm includes breakfast on Wednesday, June 6

Want to know how to get to 20nm? Want to know why? Want breakfast at DAC on June 6? This is indeed your lucky day because you can get it all done at a special DAC breakfast panel titled “The … Continue reading

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Smart analog/mixed-signal IC designs are—er—smarter. Learn how to stuff a 32-bit ARM Cortex-M core into an AMS design at DAC. Lunch included

In these days of the SoC, one chip has to do it all. That means both analog and digital processing. Now you can get a first-hand look at how successful design teams have integrated ARM Cortex-M processor cores in their … Continue reading

Posted in ARM, Cortex-M0, Cortex-M4, DAC, Mixed Signal, Silicon Realization, SoC, SoC Realization | Tagged , , , , , | 2 Comments

FREE DAC 2012 Exhibit 3-day passes. Limited quantity. Time-limited offer. Get ‘em NOW!

Want to go see the latest EDA offerings on the DAC exhibit floor but you (or your boss) can’t spring for the cash? Bummer. Atrenta, Cadence, and Springsoft feel your pain and once more, the three amigos have partnered to … Continue reading

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Is there a Denali Party 2012? The most important question at DAC, answered.

Yes, Virginia, there is a Denali party this year at DAC. As DAC returns to San Francisco in 2012, the Denali Party by Cadence returns to an extremely popular party venue—Ruby Skye—which bills itself as San Francisco’s Number One Nightclub. … Continue reading

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$2.50 buses from Silicon Valley to DAC! FREE WiFi. But you need to get a ticket. Hurry. Seats are limited

DAC takes place in San Francisco at Moscone Center. You are in Silicon Valley. It’s a classic Point A to Point B problem. Solve the problem for pocket change this year. Buses with FREE on-board WiFi will run from the … Continue reading

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What will EDA and chip design look like in the year 2020? Prognostications from the ICCAD panel

Last night, half a dozen ICCAD panelists attacked the topic “2020 Vision: What the recent history of EDA will look like in nine years.” That’s such a convoluted and hard-to-parse title that the panelists chose to discuss the state of … Continue reading

Posted in 20nm, 28nm, 3D, DAC, Design Abstraction, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , | 4 Comments

Latest episode of Hogan’s Heroes at DAC 2011 answers question: “What do EDA’s customers want?”

Jim Hogan’s annual “Hogan’s Heroes” DAC Pavilion Panel rocked as usual. This year, Hogan invited three panelists: Grant Pierce (Sonics), Jack Harding (eSilicon), and Ajoy Bose (Atrenta). All four of these people spend a lot of time thinking about the … Continue reading

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Perennial talent competitor Dave Crohn wins “EDA360’s got Talent” competition at the DAC 2011 Denali Party

Persistence paid off on Tuesday night as Dave Crohn (Broadcom) sang Bryan Adams’ 1984 hit song “Summer of ‘69” to win the “EDA360’s Got Talent” competition at the Denali Party sponsored by Cadence this year at DAC. Crohn’s sleeveless t-shirt … Continue reading

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Globalfoundries, LSI Corp, and Broadcom help Editorial Director Ed Sperling give the industry a low-power report card. How did we score?

On Wednesday at DAC’s show-floor Pavilion, Low-Power Engineering’s Editorial Director Ed Sperling chaired a panel with the intent of giving the industry a report card on its low-power engineering efforts. Along with Sperling on the Pavilion platform were Andrew Brotman, … Continue reading

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EDA360 meets DAC360: Survival tips for DAC 2011

TheEDA360 Evangelist (and EDA360 Insider blogger) was at the DAC360 video booth today with EETimes’ Brian Fuller. Here are some video survival tips and industry overviews on video.  

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How many engineers does it take to spin a chip?

The title of this blog entry paraphrases a very old joke category about light bulbs but the topic is serious because it goes to the heart of the electronic industry’s profitability. EDA analyst and ur chip-design guru Gary Smith discussed … Continue reading

Posted in DAC, EDA360, Firmware, Silicon Realization, SoC Realization, System Realization | Tagged | Leave a comment

Video: Gary Smith and the Full Disclosure Blues Band Revisited open the DAC 2011 show floor playing “Goin’ Down”

I’m not sure if this song was supposed to be a comment on the future outlook for EDA, because Gary Smith showed his second longest list of “companies to see at DAC” ever (30 companies) and forecast climbing industry revenues … Continue reading

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Cadence collaboration produces TSMC Reference Flow 12.0 and Analog-Mixed-Signal (AMS) Reference Flow v2.0 for 28nm including ESL and 3D TSV DFT support

Today’s the first day of DAC and Cadence is sponsoring a 20nm development panel and lunch at the Omni Hotel adjacent to the San Diego Convention Center. At the same time, Cadence and TSMC have been cooperating on the TSMC … Continue reading

Posted in 3D, AMS, DAC, EDA360, imec, Silicon Realization, TSMC, TSV | Leave a comment

What can you do in 20nm? Now? Today? Find out at DAC. Monday. Lunch included. Free.

OK. Here’s the deal. Cadence wants you to know about the true bleeding edge in Silicon Realization. The ASIC/SoC silicon frontier’s at 20nm. FYI: 28nm is already a day late and a process node short (thanks Richard G!). Want to … Continue reading

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EDA360 goes live for DAC!

DAC is slightly more than a week away. This year, there will be a live feed from the exhibit floor with interviews hosted by EETimes’ Brian Fuller. Look for a couple of guest hosts: long-time EDA journalist and now Cadence … Continue reading

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EDA360 gets an app

One of EDA360’s core messages is that apps are now firmly in the driver seat with respect to product and chip development. So it makes sense for EDA360 to have an app, doesn’t it? Now there is one. It’s for … Continue reading

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20nm or free lunch on Monday at DAC? How about both?

Late, late notice. I know. Mea culpa. But you’ll forgive me when you hear what’s in store for you at DAC on Monday. Cadence is organizing a panel on 20nm technology that includes lunch. How cool is that? The panelists … Continue reading

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