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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 3D Thursday: Micron to present Hybrid Memory Cube status at EDPS in Monterey, April 6—there’s a lot of news
- Moore’s Law: Wanted, Dead or Alive
- EDA VC Jim Hogan to connect the dots between user experience and SoC Realization at EDPS in April
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
- Cadence announces synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP
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Category Archives: Design Abstraction
20nm design: What have we learned so far?
Even if you are not currently considering 20nm design, you owe it to yourself to download and read a new 9-page White Paper titled “A Call to Action: How 20nm Will Change IC Design” to learn about some tectonic shifts … Continue reading
High-level synthesis, C versus assembly code, and Leibson’s Law
Years ago, when I was Editor-in-Chief of EDN Magazine, I coined (but did not name) Leibson’s Law: “It takes 10 years for any disruptive technology to become pervasive in the design community.” I was reminded of that observation while reading … Continue reading
Posted in Design Abstraction, EDA360, SoC, SoC Realization, System Realization, SystemC
Tagged ASIC, High-level synthesis, LinkedIn, SoC, SystemC
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Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm
This week at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote covering the industry’s challenges and progress at 20nm and … Continue reading
Posted in 10nm, 14nm, 20nm, 28nm, Design Abstraction, Design Intent, DFM, Double Patterning, EDA360, IBM, Silicon Realization
Tagged 10nm, 14nm, 20nm, 28nm, extraction, FinFET, ISQED, layout, parasitic
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Latest version of SystemC, IEEE 1666-2011, now supports TLM 2.0
Chocolate and peanut butter go together. So do SystemC and transaction-level modeling. Just not officially. Until now. Earlier this month, the IEEE Standards Board approved a revision to the IEEE 1666 SystemC standard to bring the widely used OSCI (Open … Continue reading
Posted in Design Abstraction, EDA360, SoC Realization, System Realization, SystemC, TLM
Tagged Accellera, EDA, IEEE 1666, OSCI, SoC Realization, SystemC, TLM
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What will EDA and chip design look like in the year 2020? Prognostications from the ICCAD panel
Last night, half a dozen ICCAD panelists attacked the topic “2020 Vision: What the recent history of EDA will look like in nine years.” That’s such a convoluted and hard-to-parse title that the panelists chose to discuss the state of … Continue reading
Posted in 20nm, 28nm, 3D, DAC, Design Abstraction, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged TSMC, Xilinx Virtex-7 2000T FPGA
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Learn how an analog design flow can boost your IC design productivity…FREE (Breakfast and Lunch too!)
You’ve got just a few days only before the new series of free technical seminars on analog design flows for analog, mixed-signal, and custom designs can boost your team’s design productivity. The key to boosting design productivity is reducing design … Continue reading
Posted in Design Abstraction, Design Convergence, Design Intent, EDA360, Silicon Realization
Tagged Analog, Mixed Signal
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“Welcome to the era of Smart Devices”says Intel’s Gadi Singer. Are you ready for the design competition?
Intel’s Gadi Singer (vice president and general manager of Intel’s SoC Enabling Group) gave the keynote presentation at DAC 2011 yesterday and he discussed the evolution of electronic devices into vehicles that deliver experiences. To do this, these devices must … Continue reading
“Professor” Aart de Geus gives latest Techonomics lecture on collaboration and System Realization at the Semico Summit in Scottsdale
Last week, Synopsys Chairman of the Board and CEO Aart de Geus gave a keynote at the Semico Summit in Scottsdale. His topics were “Techonomics,” collaboration, and systemic complexity. Techonomics is de Geus’ name for the fusion of technology and … Continue reading
Posted in Apps, Design Abstraction, Design Convergence, Design Intent, Ecosystem, EDA360, System Realization
Tagged Aart de Geus, Semico Summit, Synopsys
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What’s driving 3D IC design? Do 2D EDA tools need a total overhaul to support 3D design?
The Electronic Design Process Symposium (EDPS) held last week in Monterey devoted most of Friday to a discussion of 3D design. I’ll be devoting several EDA360 Insider blog entries to this important topic. Today’s entry summarizes the presentation by Rahul … Continue reading
