Category Archives: Design Intent

Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm

This week at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote covering  the industry’s challenges and progress at 20nm and … Continue reading

Posted in 10nm, 14nm, 20nm, 28nm, Design Abstraction, Design Intent, DFM, Double Patterning, EDA360, IBM, Silicon Realization | Tagged , , , , , , , , | Leave a comment

Learn how an analog design flow can boost your IC design productivity…FREE (Breakfast and Lunch too!)

You’ve got just a few days only before the new series of free technical seminars on analog design flows for analog, mixed-signal, and custom designs can boost your team’s design productivity. The key to boosting design productivity is reducing design … Continue reading

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Posted in Design Abstraction, Design Convergence, Design Intent, EDA360, Silicon Realization | Tagged , | Leave a comment

“Welcome to the era of Smart Devices”says Intel’s Gadi Singer. Are you ready for the design competition?

Intel’s Gadi Singer (vice president and general manager of Intel’s SoC Enabling Group) gave the keynote presentation at DAC 2011 yesterday and he discussed the evolution of electronic devices into vehicles that deliver experiences. To do this, these devices must … Continue reading

Posted in Android, Design Abstraction, Design Convergence, Design Intent, EDA360, Silicon Realization, SoC Realization, System Realization | Tagged | Leave a comment

“Professor” Aart de Geus gives latest Techonomics lecture on collaboration and System Realization at the Semico Summit in Scottsdale

Last week, Synopsys Chairman of the Board and CEO Aart de Geus gave a keynote at the Semico Summit in Scottsdale. His topics were “Techonomics,” collaboration, and systemic complexity. Techonomics is de Geus’ name for the fusion of technology and … Continue reading

Posted in Apps, Design Abstraction, Design Convergence, Design Intent, Ecosystem, EDA360, System Realization | Tagged , , | Leave a comment

What’s driving 3D IC design? Do 2D EDA tools need a total overhaul to support 3D design?

The Electronic Design Process Symposium (EDPS) held last week in Monterey devoted most of Friday to a discussion of 3D design. I’ll be devoting several EDA360 Insider blog entries to this important topic. Today’s entry summarizes the presentation by Rahul … Continue reading

Posted in 3D, Design Abstraction, Design Convergence, Design Intent, EDA360, Low Power, Packaging, Silicon Realization, SoC Realization, System Realization, Verification | Leave a comment

The critical need for expressing design intent within EDA

Mark Waller, VP of Engineering at Pulsic, just published a great article on design constraints on the chipdesignmag.com Web site. (See “It’s Time for Standard Design Constraints for Custom Design”.) Design constraints go by another name in the EDA360 vision, … Continue reading

Posted in Design Intent, EDA360, Silicon Realization | 2 Comments