Category Archives: DFM

Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm

This week at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote covering  the industry’s challenges and progress at 20nm and … Continue reading

Posted in 10nm, 14nm, 20nm, 28nm, Design Abstraction, Design Intent, DFM, Double Patterning, EDA360, IBM, Silicon Realization | Tagged , , , , , , , , | Leave a comment

Still baffled by “in-design” DFM signoff for SoC and Silicon Realization? Read this

Richard Goering has just published a detailed analysis of “in-design” DFM signoff and how it can accelerate chip implementation. Heck, it can prevent the usual fire drill that occurs just before tapeout; Instead of facing more than 100 problems that … Continue reading

Posted in DFM, EDA360, Silicon Realization, SoC, SoC Realization | 1 Comment