Category Archives: Double Patterning

3D Thursday: My breakfast with IBM’s Gary Patton leads to a discussion of 20nm and 14nm IC design

Yesterday I moderated a panel on 2(x)nm success at DAC and one of the panelists was Dr. Gary Patton, VP of IBM’s Semiconductor Research and Development Center in East Fishkill, NY. I’ve heard Dr. Patton speak before and he knows … Continue reading

Posted in 14nm, 20nm, 28nm, Double Patterning, EDA360, EUV, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , , | Leave a comment

What are the challenges of EUV lithography and the issues surrounding double patterning? CDNLive! presentation provides details.

Richard Goering has just published an excellent blog post on double patterning for 20nm and 14nm process geometries in his blog Industry Insights. The post is based on a paper presented by IBM Distinguished Engineer Lars Liebman at the recent … Continue reading

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Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm

This week at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote covering  the industry’s challenges and progress at 20nm and … Continue reading

Posted in 10nm, 14nm, 20nm, 28nm, Design Abstraction, Design Intent, DFM, Double Patterning, EDA360, IBM, Silicon Realization | Tagged , , , , , , , , | Leave a comment

Here’s more food for thought regarding 20nm design. Do you know what it takes?

One week ago, I described some of the 20nm process node benefits and challenges discussed in Wei Lii Tan’s presentation at the recent Global Technology Conference. (See “Just how high is the 20nm design mountain of challenges?”) Now Richard Goering … Continue reading

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