Search EDA360 Insider
Hey!!! Subscribe now to the EDA360 Insider!
-
Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud
- 2.5D
- 3D
- 3D IC
- 20nm
- 28nm
- 32nm
- 40nm
- Agilent
- Altera
- AMD
- Analog
- Android
- Apple
- ARM
- ARM architecture
- ARM Cortex-A15
- ASIC
- Broadcom
- Cadence
- Canon
- Cortex
- Cortex-A15
- Cortex-M0
- DAC
- Dave Jones
- DDR3
- DDR4
- Double Patterning
- EDA
- EDPS
- Field-programmable gate array
- FinFET
- Flash
- Flash memory
- FPGA
- Freescale
- Freescale Semiconductor
- GlobalFoundries
- IBM
- Intel
- IP
- iPad
- iPhone
- JEDEC
- Jim Hogan
- Kinect
- Linux
- Low Power
- Lytro
- microcontroller
- Micron
- Microsoft
- Mixed Signal
- Multi-core processor
- Nvidia
- OrCAD
- pcb
- Printed circuit board
- Qualcomm
- Robot
- Samsung
- SDRAM
- Snapdragon
- SoC
- STMicroelectronics
- SystemC
- Texas Instruments
- TI
- TSMC
- USB
- verification
- video
- Wide I/O
- Xilinx
Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 10 ways to get your EDA tools to run faster, smoother, and longer
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Friday Video: Ready for a little mobile phone teardown archaeology? Dave Jones compares state of the art in 1994 (Motorola) with an evolved 2000 (Nokia)
- 20nm design: What have we learned so far?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
Download the EDA360 Vision Paper here:
Category Archives: Globalfoundries
Friday Video: Luigi Capodieci, a fellow at GLOBALFOUNDRIES, talks 20nm and below, EUV, FINFETs, and the state of the foundry business
Be sure to watch this excellent 13-minute interview done by Mark LePedus starring Luigi Capodieci, a fellow with GLOBALFOUNDRIES, to get a close-up-and-personal look at the state of the foundry business (it’s not dying), 20nm design, EUV in the wings, … Continue reading
Posted in 14nm, 20nm, EUV, Globalfoundries, Silicon Realization
Tagged Extreme ultraviolet, FinFET, GlobalFoundries
Leave a comment
3D Thursday: GLOBALFOUNDRIES adds TSV capability for 28nm and 20nm die to Fab 8 in Saratoga County, New York
Customers’ clamor for 3D IC assembly capability and die with TSVs (through-silicon vias) has apparently gotten loud enough to cause a change of game plan for GLOBALFOUNDRIES, which announced today that it is spending “tens of millions of dollars” to … Continue reading
Common Platform: Why do these companies (IBM, Samsung, GLOBALFOUNDRIES) collaborate?
Ana Hunter, Foundry Services VP at Samsung Semiconductor, had the honor of kicking off the Global Technology Forum in Silicon Valley. She decided to devote her short intro speech to answering the basic question about the Common Platform—a partnership among … Continue reading
Posted in EDA360, Globalfoundries, Samsung, Silicon Realization
Tagged Common Platform, Global Technology Forum, GlobalFoundries, IBM, Samsung
Leave a comment
Want to know what’s going to happen at 20nm, 14nm, and beyond? A few answers from Frank Leu of Cadence
Last week at the Global Technology Forum held at the Santa Clara Convention Center in Silicon Valley, Cadence VP of R&D Frank Leu discussed the things we’ve learned about 20nm IC manufacturing, what we are learning about 14nm, and where … Continue reading
Posted in 14nm, 20nm, 28nm, EDA360, Globalfoundries, Samsung, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 14nm, 20nm, 28nm, Cadence, IBM, In-Design, Samsung
2 Comments
Where is the mainstream IC process technology today? 28nm? 40nm? 65nm?
EDA companies like Cadence focus on developing the latest tools for bleeding-edge process technologies—28nm and 20nm today—and that’s been the emphasis of my blog posts from last week’s Global technology Conference (GTC). However, there was one panel at the conference … Continue reading
Posted in EDA360, Globalfoundries, Silicon Realization
Tagged 130nm, 180nm, 20nm, 28nm, 32nm, 40nm, 65nm, 90nm
Leave a comment
Collaboration is key to making DFM work at 28nm and below
At the final presentation I attended at last week’s Global Technology Forum, Manoj Chacko from Cadence discussed how to get “everything you’re entitled to” with In-Design DFM (Design for Manufacturing). Two of the key yield detractors Chacko discussed are yield … Continue reading
Posted in EDA360, Globalfoundries, Silicon Realization, SoC Realization
Tagged GlobalFoundries
Leave a comment
Just how high is the 20nm design mountain of challenges?
One of the last presentations at last week’s Global Technology Conference was the talk on 20nm design challenges presented by Wei Lii Tan of Cadence. Tan first summarized the benefits of the 20nm process node relative to 28nm: 30-50% better … Continue reading
Posted in ARM, EDA360, Globalfoundries, Silicon Realization, SoC Realization
Tagged Applied Materials, Double Patterning
Leave a comment
GLOBALFOUNDRIES talks FinFETs, EUV, 14nm, ETSOI. Any other bleeding-edge chipmaking terms you wanted to hear?
Near the end of his Global Technology Conference presentation last week, Senior VP of Technology and R&D Gregg Bartlett jumped to the future—namely 2014 to 2015. By then, GLOBALFOUNDRIES plans to be implementing the second production phase for its 20nm … Continue reading
Posted in EDA360, Globalfoundries, Silicon Realization
Tagged 14nm, 20nm, ETSOI, EUV, FinFET
Leave a comment
How much faster will 20nm be?
I’ve been discussing Gregg Bartlett’s talk at this week’s Global Technology Conference and thought I’d focus this blog post on one graphic: As I mentioned in my last post, “GLOBALFOUNDRIES’ 28nm process comes in three flavors. Which is right for you?”, … Continue reading
GLOBALFOUNDRIES’ 28nm process comes in three flavors. Which is right for you?
This week at the Global Technology conference sponsored by GLOBALFOUNDRIES and its partners, Gregg Bartlett, Senior VP of Technology and Engineering at GLOBALFOUNDRIES, discussed the three flavors of the foundry’s 28nm IC manufacturing process. The 28nm-HPP (high-performance plus) process is … Continue reading
Want to know the three lessons for GLOBALFOUNDRIES from its 28nm high-K, metal-gate development?
Yesterday, I attended the Global Technology Conference, a chip-making extravaganza underwritten by GLOBALFOUNDRIES and its partners. Got several blog posts to write about this information-packed day but thought I’d start with the three lessons that GLOBALFOUNDRIES learned from its 28nm … Continue reading
Who else wants to see a 60x speedup in DFM signoff on a 28nm design?
Rambus has announced that it achieved a 60x speedup in DRC for an IP design targeting a 28nm process technology using GLOBALFOUNDRIES’ DRC+ methodology. This approach to DRC is interesting because it’s the industry’s first approach to DRC that teams … Continue reading
Posted in EDA360, Globalfoundries, Silicon Realization
Tagged 28nm, 32nm, Design rule checking, DRC, IP, Rambus
Leave a comment
Are you on a Silicon Realization team? Designing ASICs and SoCs? Then you need to attend one of the Global Technology Conferences
If you’re actively developing ASICs and SoCs, you’re in the Silicon Realization business and that means you need to gather all the information you can about the business wherever you can. Globalfoundries wants to make that task easier by inviting … Continue reading
EDA360 Insider 