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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- GLOBALFOUNDRIES’ 28nm process comes in three flavors. Which is right for you?
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- 3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D
- 3D Thursday: How about a closeup of the Avago MiniPOD optical interconnect on the Altera Optical FPGA?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- Between ASIC and microcontroller: It’s all about System Realization
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
- What would you do with a 23,000-simultaneous-thread school of piranha?...asks NVIDIA
- 3D Thursday (early): Steve’s Improbable History of 3D ICs? Six decades of 3D electronic packaging
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Category Archives: IBM
Hear IBM’s Dr. Gary Patton on the future of silicon scaling…and beyond. (Audio from The Common Technology Platform Forum keynote)
Earlier this year, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center, spoke about the future of semiconductor scaling and beyond. It was a terrific keynote speech at the Common Platform Technology Forum and was similar to … Continue reading
Posted in 10nm, 14nm, 20nm, 3D, EDA360, IBM, Silicon Realization
Tagged Common Technology Platform Forum, Gary Patton, IBM
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Moore’s Law: Wanted, Dead or Alive
Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held … Continue reading
At DAC, take the path to successful 20nm design. The same path leads to breakfast. Wednesday, June 6
If you’ve been following along—or even if you haven’t—Cadence held three 20nm Webinars last week. Perhaps you have to see it in person before you believe it. Fair enough. Here’s your chance to hear first-hand how you can develop high-yielding … Continue reading
Posted in 20nm, EDA360, IBM, Samsung, Silicon Realization, SoC, SoC Realization
Tagged 20nm, IBM, Moscone Center, Samsung
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Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm
This week at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote covering the industry’s challenges and progress at 20nm and … Continue reading
Posted in 10nm, 14nm, 20nm, 28nm, Design Abstraction, Design Intent, DFM, Double Patterning, EDA360, IBM, Silicon Realization
Tagged 10nm, 14nm, 20nm, 28nm, extraction, FinFET, ISQED, layout, parasitic
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