Category Archives: IBM

Hear IBM’s Dr. Gary Patton on the future of silicon scaling…and beyond. (Audio from The Common Technology Platform Forum keynote)

Earlier this year, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center, spoke about the future of semiconductor scaling and beyond. It was a terrific keynote speech at the Common Platform Technology Forum and was similar to … Continue reading

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Moore’s Law: Wanted, Dead or Alive

Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held … Continue reading

Posted in 20nm, 28nm, 32nm, 40nm, 65nm, EDA360, IBM, Low Power, Memory, Multicore, Packaging, TSV | Tagged , , , , , , , | 2 Comments

At DAC, take the path to successful 20nm design. The same path leads to breakfast. Wednesday, June 6

If you’ve been following along—or even if you haven’t—Cadence held three 20nm Webinars last week. Perhaps you have to see it in person before you believe it. Fair enough. Here’s your chance to hear first-hand how you can develop high-yielding … Continue reading

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Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm

This week at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote covering  the industry’s challenges and progress at 20nm and … Continue reading

Posted in 10nm, 14nm, 20nm, 28nm, Design Abstraction, Design Intent, DFM, Double Patterning, EDA360, IBM, Silicon Realization | Tagged , , , , , , , , | Leave a comment