Category Archives: imec

3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work

I recently covered the groundbreaking WIOMING 3D chip design done by CEA-Imec in conjunction with ST-Ericsson. (See “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. … Continue reading

Posted in 2.5D, 3D, EDA360, imec, SoC, SoC Realization | Tagged , , , , , , , , , , , , , , , | Leave a comment

Cadence collaboration produces TSMC Reference Flow 12.0 and Analog-Mixed-Signal (AMS) Reference Flow v2.0 for 28nm including ESL and 3D TSV DFT support

Today’s the first day of DAC and Cadence is sponsoring a 20nm development panel and lunch at the Omni Hotel adjacent to the San Diego Convention Center. At the same time, Cadence and TSMC have been cooperating on the TSMC … Continue reading

Posted in 3D, AMS, DAC, EDA360, imec, Silicon Realization, TSMC, TSV | Leave a comment